410 lines
15 KiB
ReStructuredText
410 lines
15 KiB
ReStructuredText
Yosys
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=====
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Yosys is a Free and Open Source Verilog HDL synthesis tool. It was designed
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to be highly extensible and multiplatform. In SymbiFlow toolchain,
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it is responsible for the whole synthesis process described in `FPGA Design Flow
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<./design-flow.html>`_
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It is not necessary to call Yosys directly using the SymbiFlow
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toolchain. Nevertheless, the following description, should provide
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sufficient introduction to Yosys usage inside the project.
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It is also a good starting point for a deeper understanding of the whole
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toolchain.
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Short description
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-----------------
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Yosys consists of several subsystems. Most distinguishable are the
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first and last ones used in the synthesis process, called *frontend*
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and *backend* respectively. Intermediate subsystems are called *passes*.
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The *frontend* is responsible for changing the Verilog input file into
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an internal Yosys, representation which is common for all *passes* used
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by the program. The *passes* are responsible for a variety of optimizations
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(``opt_``) and simplifications (``proc_``).
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Two *passes*, that are worth
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to mention separately are ``ABC`` and ``techmap``. The first one optimizes
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logic functions from the design and assigns obtained results into Look Up Tables
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(LUTs) of chosen width. The second mentioned *pass* - ``techmap``
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is responsible for mapping the synthesized design from Yosys internal
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blocks to the primitives used by the implementation tool.
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Recommended synthesis flows for different FPGAs are combined into
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macros i.e. ``synth_ice40`` (for Lattice iCE40 FPGA) or ``synth_xilinx``
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(for Xilinx 7-series FPGAs).
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The *backend* on the other hand, is responsible
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for converting internal Yosys representation into one of the standardized
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formats. Symbiflow uses ``.eblif`` as its output file format.
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Usage in Toolchain
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------------------
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All operations performed by Yosys are written in ``.tcl`` script. Commands used
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in the scripts are responsible for preparing output file to match with the
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expectations of other toolchain tools.
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There is no need to change it even for big designs.
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An example configuration script can be found below:
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.. code-block:: tcl
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yosys -import
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synth_ice40 -nocarry
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opt_expr -undriven
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opt_clean
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setundef -zero -params
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write_blif -attr -cname -param $::env(OUT_EBLIF)
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write_verilog $::env(OUT_SYNTH_V)
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It can be seen that this script performs a platform-specific process of
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synthesis, some optimization steps (``opt_`` commands), and writes the final file in
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``.eblif`` and Verilog formats. Yosys synthesis configuration scripts are platform-specific
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and can by found in ``<platform-dir>/yosys/synth.tcl``
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in the `Symbiflow Architecture Definitions <https://github.com/SymbiFlow/symbiflow-arch-defs>`_
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repository.
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To understand performed operations, view the log file. It is usually generated
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in the project build directory. It should be named ``top.eblif.log``.
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Output analysis
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---------------
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Input file:
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.. code-block:: verilog
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module top (
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input clk,
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output LD7,
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);
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localparam BITS = 1;
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localparam LOG2DELAY = 25;
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reg [BITS+LOG2DELAY-1:0] counter = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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end
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assign {LD7} = counter >> LOG2DELAY;
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endmodule
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after synthesis is described only with use of primitives appropriate for
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chosen platform:
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.. code-block:: verilog
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module top(clk, LD7);
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wire [25:0] _000_;
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wire _001_;
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...
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FDRE_ZINI #(
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.IS_C_INVERTED(1'h0),
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.ZINI(1'h1)
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) _073_ (
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.C(clk),
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.CE(_012_),
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.D(_000_[0]),
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.Q(counter[0]),
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.R(_013_)
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);
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...
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SR_GND _150_ (
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.GND(_062_)
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);
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assign _003_[25:0] = _000_;
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assign counter[25] = LD7;
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endmodule
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The same structure is described by the ``.eblif`` file.
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Technology mapping in SymbiFlow toolchain
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-----------------------------------------
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.. _Xilinx 7 Series FPGAs Clocking Resources User Guide: https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=38
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.. _VTR FPGA Architecture Description: https://docs.verilogtorouting.org/en/latest/arch/
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.. _techmap section in the Yosys Manual: http://www.clifford.at/yosys/files/yosys_manual.pdf#page=153
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It is important to understand the connection between the synthesis and
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implementation tools used in the SymbiFlow toolchain. As mentioned before,
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synthesis tools like Yosys take the design description from the source files
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and convert them into a netlist that consists of the primitives used by
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the implementation tool. Usually, to support multiple implementation tools,
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an additional intermediate representation of FPGA primitives is provided.
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The process of translating the primitives from the synthesis
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tool’s internal representation to the specific primitives used in the
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implementation tools is called technology mapping (or techmapping).
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Technology mapping for VPR
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--------------------------
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As mentioned before, VPR is one of the implementation tools (often referred to
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as Place & Route or P&R tools) used in SymbiFlow. By default, the SymbiFlow
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toolchain uses it during bitstream generation for, i.e., Xilinx 7-Series
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devices. Since the architecture models for this FPGA family were created from
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scratch, appropriate techmaps were needed to instruct Yosys on translating
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the primitives to the versions compatible with VPR.
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The clock buffers used in the 7-Series devices are a good example for explaining
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the techmapping process. Generally, as stated in the
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`Xilinx 7 Series FPGAs Clocking Resources User Guide`_, a designer has various
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buffer types that they can use in designs:
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- ``BUFGCTRL``
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- ``BUFG``
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- ``BUFGCE``
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- ``BUFGCE_1``
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- ``BUFGMUX``
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- ``BUFGMUX_1``
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- ``BUFGMUX_CTRL``
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Nevertheless, the actual chips consist only of the ``BUFGCTRL`` primitives,
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which are the most universal and can function as other clock buffer
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primitives from the Xilinx manual. Because of that, only one architecture model
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is required for VPR. The rest of the primitives is mapped to this general
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buffer during the techmapping process. The model of ``BUFGCTRL`` primitive used
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by VPR is called ``BUFGCTR_VPR`` (More information about the architecture
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modeling in VPR can be found in the `VTR FPGA Architecture Description`_).
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Support for particular primitive in VTR consist of two files:
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- Model XML (``xxx.model.xml``) - Contains general information about
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the module's input and output ports and their relations.
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- Physical Block XML (``xxx.pb_type.xml``) - Describes the actual layout of the
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primitive, with information about the timings, internal connections, etc.
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Below you can see the pb_type XML for ``BUFGCTRL_VPR`` primitive:
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.. code-block:: xml
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<!-- Model of BUFG group in BUFG_CLK_TOP/BOT -->
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<pb_type name="BLK-TL-BUFGCTRL" xmlns:xi="http://www.w3.org/2001/XInclude">
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<output name="O" num_pins="1"/>
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<input name="CE0" num_pins="1"/>
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<input name="CE1" num_pins="1"/>
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<clock name="I0" num_pins="1"/>
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<clock name="I1" num_pins="1"/>
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<input name="IGNORE0" num_pins="1"/>
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<input name="IGNORE1" num_pins="1"/>
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<input name="S0" num_pins="1"/>
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<input name="S1" num_pins="1"/>
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<mode name="EMPTY">
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<pb_type name="empty" blif_model=".latch" num_pb="1" />
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<interconnect />
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</mode>
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<mode name="BUFGCTRL">
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<pb_type name="BUFGCTRL_VPR" blif_model=".subckt BUFGCTRL_VPR" num_pb="1">
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<output name="O" num_pins="1"/>
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<input name="CE0" num_pins="1"/>
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<input name="CE1" num_pins="1"/>
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<clock name="I0" num_pins="1"/>
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<clock name="I1" num_pins="1"/>
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<input name="IGNORE0" num_pins="1"/>
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<input name="IGNORE1" num_pins="1"/>
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<input name="S0" num_pins="1"/>
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<input name="S1" num_pins="1"/>
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<metadata>
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<meta name="fasm_params">
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ZPRESELECT_I0 = ZPRESELECT_I0
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ZPRESELECT_I1 = ZPRESELECT_I1
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IS_IGNORE0_INVERTED = IS_IGNORE0_INVERTED
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IS_IGNORE1_INVERTED = IS_IGNORE1_INVERTED
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ZINV_CE0 = ZINV_CE0
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ZINV_CE1 = ZINV_CE1
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ZINV_S0 = ZINV_S0
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ZINV_S1 = ZINV_S1
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</meta>
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</metadata>
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</pb_type>
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<interconnect>
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<direct name="O" input="BUFGCTRL_VPR.O" output="BLK-TL-BUFGCTRL.O"/>
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<direct name="CE0" input="BLK-TL-BUFGCTRL.CE0" output="BUFGCTRL_VPR.CE0"/>
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<direct name="CE1" input="BLK-TL-BUFGCTRL.CE1" output="BUFGCTRL_VPR.CE1"/>
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<direct name="I0" input="BLK-TL-BUFGCTRL.I0" output="BUFGCTRL_VPR.I0"/>
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<direct name="I1" input="BLK-TL-BUFGCTRL.I1" output="BUFGCTRL_VPR.I1"/>
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<direct name="IGNORE0" input="BLK-TL-BUFGCTRL.IGNORE0" output="BUFGCTRL_VPR.IGNORE0"/>
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<direct name="IGNORE1" input="BLK-TL-BUFGCTRL.IGNORE1" output="BUFGCTRL_VPR.IGNORE1"/>
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<direct name="S0" input="BLK-TL-BUFGCTRL.S0" output="BUFGCTRL_VPR.S0"/>
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<direct name="S1" input="BLK-TL-BUFGCTRL.S1" output="BUFGCTRL_VPR.S1"/>
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</interconnect>
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<metadata>
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<meta name="fasm_features">
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IN_USE
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</meta>
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</metadata>
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</mode>
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</pb_type>
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A correctly prepared techmap for any VPR model contains a declaration of
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the module that should be substituted. Inside the module declaration, one
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should provide a necessary logic and instantiate another module that
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will substitute its original version. Additionally, all equations within
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a techmap that are not used directly in a module instantiation should evaluate
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to a constant value. Therefore most of the techmaps use additional constant
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parameters to modify the signals attached to the instantiated module.
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Here is a piece of a techmap, which instructs Yosys to convert
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a ``BUFG`` primitive to the ``BUFGCTRL_VPR``. In this case, the techmaping process
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consists of two steps. Firstly, the techmap shows how to translate the ``BUFG``
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primitive to the ``BUFGCTRL``. Then how to translate the ``BUFGCTRL`` to
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the ``BUFGCTRL_VPR``:
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.. code-block:: verilog
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module BUFG (
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input I,
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output O
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);
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BUFGCTRL _TECHMAP_REPLACE_ (
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.O(O),
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.CE0(1'b1),
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.CE1(1'b0),
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.I0(I),
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.I1(1'b1),
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.IGNORE0(1'b0),
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.IGNORE1(1'b1),
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.S0(1'b1),
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.S1(1'b0)
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);
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endmodule
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module BUFGCTRL (
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output O,
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input I0, input I1,
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input S0, input S1,
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input CE0, input CE1,
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input IGNORE0, input IGNORE1
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);
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parameter [0:0] INIT_OUT = 1'b0;
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parameter [0:0] PRESELECT_I0 = 1'b0;
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parameter [0:0] PRESELECT_I1 = 1'b0;
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parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
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parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
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parameter [0:0] IS_CE0_INVERTED = 1'b0;
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parameter [0:0] IS_CE1_INVERTED = 1'b0;
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parameter [0:0] IS_S0_INVERTED = 1'b0;
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parameter [0:0] IS_S1_INVERTED = 1'b0;
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parameter _TECHMAP_CONSTMSK_IGNORE0_ = 0;
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parameter _TECHMAP_CONSTVAL_IGNORE0_ = 0;
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parameter _TECHMAP_CONSTMSK_IGNORE1_ = 0;
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parameter _TECHMAP_CONSTVAL_IGNORE1_ = 0;
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parameter _TECHMAP_CONSTMSK_CE0_ = 0;
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parameter _TECHMAP_CONSTVAL_CE0_ = 0;
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parameter _TECHMAP_CONSTMSK_CE1_ = 0;
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parameter _TECHMAP_CONSTVAL_CE1_ = 0;
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parameter _TECHMAP_CONSTMSK_S0_ = 0;
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parameter _TECHMAP_CONSTVAL_S0_ = 0;
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parameter _TECHMAP_CONSTMSK_S1_ = 0;
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parameter _TECHMAP_CONSTVAL_S1_ = 0;
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localparam [0:0] INV_IGNORE0 = (
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_TECHMAP_CONSTMSK_IGNORE0_ == 1 &&
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_TECHMAP_CONSTVAL_IGNORE0_ == 0 &&
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IS_IGNORE0_INVERTED == 0);
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localparam [0:0] INV_IGNORE1 = (
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_TECHMAP_CONSTMSK_IGNORE1_ == 1 &&
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_TECHMAP_CONSTVAL_IGNORE1_ == 0 &&
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IS_IGNORE1_INVERTED == 0);
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localparam [0:0] INV_CE0 = (
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_TECHMAP_CONSTMSK_CE0_ == 1 &&
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_TECHMAP_CONSTVAL_CE0_ == 0 &&
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IS_CE0_INVERTED == 0);
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localparam [0:0] INV_CE1 = (
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_TECHMAP_CONSTMSK_CE1_ == 1 &&
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_TECHMAP_CONSTVAL_CE1_ == 0 &&
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IS_CE1_INVERTED == 0);
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localparam [0:0] INV_S0 = (
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_TECHMAP_CONSTMSK_S0_ == 1 &&
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_TECHMAP_CONSTVAL_S0_ == 0 &&
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IS_S0_INVERTED == 0);
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localparam [0:0] INV_S1 = (
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_TECHMAP_CONSTMSK_S1_ == 1 &&
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_TECHMAP_CONSTVAL_S1_ == 0 &&
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IS_S1_INVERTED == 0);
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BUFGCTRL_VPR #(
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.INIT_OUT(INIT_OUT),
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.ZPRESELECT_I0(PRESELECT_I0),
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.ZPRESELECT_I1(PRESELECT_I1),
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.IS_IGNORE0_INVERTED(!IS_IGNORE0_INVERTED ^ INV_IGNORE0),
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.IS_IGNORE1_INVERTED(!IS_IGNORE1_INVERTED ^ INV_IGNORE1),
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.ZINV_CE0(!IS_CE0_INVERTED ^ INV_CE0),
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.ZINV_CE1(!IS_CE1_INVERTED ^ INV_CE1),
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.ZINV_S0(!IS_S0_INVERTED ^ INV_S0),
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.ZINV_S1(!IS_S1_INVERTED ^ INV_S1)
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) _TECHMAP_REPLACE_ (
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.O(O),
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.CE0(CE0 ^ INV_CE0),
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.CE1(CE1 ^ INV_CE1),
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.I0(I0),
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.I1(I1),
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.IGNORE0(IGNORE0 ^ INV_IGNORE0),
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.IGNORE1(IGNORE1 ^ INV_IGNORE1),
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.S0(S0 ^ INV_S0),
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.S1(S1 ^ INV_S1)
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);
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endmodule
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.. note::
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All SymbiFlow techmaps for Xilinx 7-Series devices use special inverter
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logic that converts constant 0 signals at the BEL to constant-1 signals
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at the site. This behavior is desired since VCC is the default signal in
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7-Series and US/US+ devices. The presented solution matches the conventions
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used by the vendor tools and gives the opportunity to validate generated
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bitstreams with fasm2bels and Vivado.
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Yosys provides special techmapping naming conventions for wires,
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parameters, and modules. The special names that start with ``_TECHMAP_``
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can be used to force certain behavior during the techmapping process.
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Currently, the following special names are used in SymbiFlow techmaps:
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- ``_TECHMAP_REPLACE_`` is used as a name for an instantiated module, which will
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replace the one used in the original design. This special name causes
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the instantiated module to inherit the name and all attributes
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from the module that is being replaced.
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- ``_TECHMAP_CONSTMSK_<port_name>_`` and ``_TECHMAP_CONSTVAL_<port_name>_``
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are used together as names of parameters. The ``_TECHMAP_CONSTMASK_<port_name>_``
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has a length of the input signal. Its bits take the value 1 if
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the corresponding signal bit has a constant value, or 0 otherwise.
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The ``_TECHMAP_CONSTVAL_<port_name>_`` bits store the actual constant signal
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values when the ``_TECHMAP_CONSTMASK_<port_name>_`` is equal to 1.
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More information about special wire, parameter, and module names can be found in
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`techmap section in the Yosys Manual`_.
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.. note::
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Techmapping can be used not only to change the names of the primitives
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but primarily to match the port declarations and express the logic behind
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the primitive substitution:
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.. verilog:module:: module BUFG (output O, input I)
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.. verilog:module:: module BUFGCTRL (output O, input CE0, input CE1, input I0, input I1, input IGNORE0, input IGNORE1, input S0, input S1)
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More information
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----------------
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Additional information about Yosys can be found on the `Yosys Project Website
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<http://www.clifford.at/yosys/>`_ , or in `Yosys Manual
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<http://www.clifford.at/yosys/files/yosys_manual.pdf>`_. You can also compile
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one of the tests described in Getting Started section and watch the log file
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to understand which operations are performed by Yosys.
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