mirror of
https://github.com/chipsalliance/f4pga.git
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85 lines
2.7 KiB
Python
85 lines
2.7 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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from pathlib import Path
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from f4pga.flows.common import vpr_specific_values, noisy_warnings, vpr as common_vpr, VprArgs
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from f4pga.flows.module import Module, ModuleContext
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DEFAULT_TIMING_RPT = "pre_pack.report_timing.setup.rpt"
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DEFAULT_UTIL_RPT = "packing_pin_util.rpt"
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class PackModule(Module):
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def map_io(self, ctx: ModuleContext):
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epath = Path(ctx.takes.eblif)
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build_dir = epath.parent
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return {
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"net": str(epath.with_suffix(".net")),
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"util_rpt": str(build_dir / DEFAULT_UTIL_RPT),
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"timing_rpt": str(build_dir / DEFAULT_TIMING_RPT),
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}
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def execute(self, ctx: ModuleContext):
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noisy_warnings(ctx.values.device)
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build_dir = Path(ctx.outputs.net).parent
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yield "Packing with VPR..."
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common_vpr(
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"pack",
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VprArgs(
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share=ctx.share,
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eblif=ctx.takes.eblif,
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arch_def=ctx.values.arch_def,
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lookahead=ctx.values.rr_graph_lookahead_bin,
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rr_graph=ctx.values.rr_graph_real_bin,
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place_delay=ctx.values.vpr_place_delay,
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device_name=ctx.values.vpr_grid_layout_name,
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vpr_options=ctx.values.vpr_options if ctx.values.vpr_options else {},
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sdc_file=ctx.takes.sdc,
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),
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cwd=build_dir,
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)
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og_log = build_dir / "vpr_stdout.log"
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yield "Moving/deleting files..."
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if ctx.outputs.pack_log:
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og_log.rename(ctx.outputs.pack_log)
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else:
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og_log.unlink()
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if ctx.outputs.timing_rpt:
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(build_dir / DEFAULT_TIMING_RPT).rename(ctx.outputs.timing_rpt)
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if ctx.outputs.util_rpt:
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(build_dir / DEFAULT_UTIL_RPT).rename(ctx.outputs.util_rpt)
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def __init__(self, _):
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self.name = "pack"
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self.no_of_phases = 2
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self.takes = ["eblif", "sdc?"]
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self.produces = ["net", "util_rpt", "timing_rpt", "pack_log!"]
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self.values = [
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"device",
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] + vpr_specific_values()
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ModuleClass = PackModule
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