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Synthesis</a>
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<section id="synthesis">
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<h1 id="flows-synthesis--page-root">Synthesis<a class="headerlink" href="#flows-synthesis--page-root" title="Link to this heading">¶</a></h1>
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<p>Synthesis is the process of converting input Verilog file into a netlist,
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which describes the connections between different block available on the
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desired FPGA chip. However, it is worth to notice that these are only
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logical connections. So the synthesized model is only a draft of the final
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design, made with the use of available resources.</p>
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<section id="rtl-generation">
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<h2 id="rtl-generation">RTL Generation<a class="headerlink" href="#rtl-generation" title="Link to this heading">¶</a></h2>
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<p>the input Verilog file is often really complicated. Usually it is written in
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a way that it is hard to distinguish the digital circuit standing behind
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the implemented functionality. Designers often use a so-called
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<em>Behavioral Level</em> of abstraction, in their designs, which means that the whole
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description is mostly event-driven. In Verilog, support for behavioral models
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is made with use of <code class="docutils literal notranslate"><span class="pre">always</span></code> statements.</p>
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<p>However, FPGA mostly consist of Look Up Tables (LUT) and flip-flops.
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Look Up Tables implement only the functionality of logic gates.
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Due to that, the synthesis process has to convert the complicated
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Behavioral model to a simpler description.</p>
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<p>Firstly, the design is described in terms of registers and logical operations.
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This is the so-called <em>Register-Transfer Level</em> (<em>RTL</em>).
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Secondly, in order to simplify the design even more, some complex logic is
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rewritten in the way that the final result contain only logic gates
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and registers. This model is on <em>Logical Gate level</em> of abstraction.</p>
|
||
<p>The process of simplification is quite complicated, because of that it often
|
||
demands additional simulations between mentioned steps to prove that the input
|
||
design is equivalent to its simplified form.</p>
|
||
</section>
|
||
<section id="technology-mapping">
|
||
<h2 id="technology-mapping">Technology mapping<a class="headerlink" href="#technology-mapping" title="Link to this heading">¶</a></h2>
|
||
<p>FPGAs from different architectures may have different architecture. For example,
|
||
they may contain some complicated functional blocks (i.e. RAM, DSP blocks)
|
||
and even some of the basic blocks like LUT tables and flip-flops may vary
|
||
between chips. Because of that, there is a need to describe the final design
|
||
in terms of platform-specific resources. This is the next step in the process
|
||
of synthesis. The simplified description containing i.e. logic gates, flip-flops
|
||
and a few more complicated blocks like RAM is taken and used “general” blocks
|
||
are substituted with that physically located in the chosen FPGA.
|
||
The vendor-specific definitions of these blocks are often located
|
||
in a separate library.</p>
|
||
</section>
|
||
<section id="optimization">
|
||
<h2 id="optimization">Optimization<a class="headerlink" href="#optimization" title="Link to this heading">¶</a></h2>
|
||
<p>Optimization is the key factor that allows to better utilize resources
|
||
of an FPGA. There are some universal situations in which the design
|
||
can be optimized, for example by substituting a bunch of logic gates
|
||
in terms of fewer, different gates. However, some operations can be performed
|
||
only after certain steps i.e. after technology mapping.
|
||
As a result, optimization is an integral part of most of the synthesis steps.</p>
|
||
</section>
|
||
</section>
|
||
|
||
|
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