49 lines
1.8 KiB
YAML
49 lines
1.8 KiB
YAML
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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{
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# General ------------------------------------------------------------------
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -2, # FPGA speedgrade
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"memtype": "DDR4", # DRAM type
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# PHY ----------------------------------------------------------------------
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"cmd_latency": 0, # Command additional latency
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"sdram_module": "EDY4016A", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 8, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "USDDRPHY", # Type of FPGA PHY
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# Electrical ---------------------------------------------------------------
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"rtt_nom": "80ohm", # Nominal termination
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"rtt_wr": "80ohm", # Write termination
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"ron": "34ohm", # Output driver impedance
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 200e6, # Input clock frequency
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"sys_clk_freq": 150e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"axi_0" : {
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"type": "axi",
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"id_width": 32,
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},
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"wishbone_0" : {
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"type": "wishbone",
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},
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"native_0" : {
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"type": "native",
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},
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"fifo_0" : {
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"type": "fifo",
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"base": 0x00000000,
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"depth": 0x01000000,
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},
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},
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}
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