369 lines
14 KiB
Plaintext
369 lines
14 KiB
Plaintext
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/****************************************************************************************
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*
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* File Name: subtest.vh
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*
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* Description: Micron SDRAM DDR3 (Double Data Rate 3)
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* This file is included by tb.v
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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initial begin : test
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parameter [31:0] REP = DQ_BITS/8.0;
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reg [BA_BITS-1:0] r_bank;
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reg [ROW_BITS-1:0] r_row;
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reg [COL_BITS-1:0] r_col;
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reg [BL_MAX*DQ_BITS-1:0] r_data;
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integer r_i, r_j;
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real original_tck;
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reg [8*DQ_BITS-1:0] d0, d1, d2, d3;
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d0 = {
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{REP{8'h07}}, {REP{8'h06}}, {REP{8'h05}}, {REP{8'h04}},
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{REP{8'h03}}, {REP{8'h02}}, {REP{8'h01}}, {REP{8'h00}}
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};
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d1 = {
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{REP{8'h17}}, {REP{8'h16}}, {REP{8'h15}}, {REP{8'h14}},
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{REP{8'h13}}, {REP{8'h12}}, {REP{8'h11}}, {REP{8'h10}}
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};
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d2 = {
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{REP{8'h27}}, {REP{8'h26}}, {REP{8'h25}}, {REP{8'h24}},
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{REP{8'h23}}, {REP{8'h22}}, {REP{8'h21}}, {REP{8'h20}}
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};
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d3 = {
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{REP{8'h37}}, {REP{8'h36}}, {REP{8'h35}}, {REP{8'h34}},
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{REP{8'h33}}, {REP{8'h32}}, {REP{8'h31}}, {REP{8'h30}}
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};
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rst_n <= 1'b0;
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cke <= 1'b0;
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cs_n <= 1'b1;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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ba <= {BA_BITS{1'bz}};
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a <= {ADDR_BITS{1'bz}};
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odt_out <= 1'b0;
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dq_en <= 1'b0;
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dqs_en <= 1'b0;
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// POWERUP SECTION
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power_up;
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// INITIALIZE SECTION
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zq_calibration (1); // perform Long ZQ Calibration
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load_mode (3, 14'b00000000000000); // Extended Mode Register (3)
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nop (tmrd-1);
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load_mode (2, {14'b00001000_000_000} | mr_cwl<<3); // Extended Mode Register 2 with DCC Disable
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nop (tmrd-1);
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load_mode (1, 14'b0000010110); // Extended Mode Register with DLL Enable, AL=CL-1
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nop (tmrd-1);
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load_mode (0, {14'b0_0_000_1_0_000_1_0_00} | mr_wr<<9 | mr_cl<<2); // Mode Register with DLL Reset
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nop (max(TDLLK,TZQINIT));
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odt_out <= 1; // turn on odt
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nop (10);
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// Random Act -> Write -> Read -> Precharge
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for (r_i = 0; r_i < 2048; r_i = r_i + 1) begin
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r_bank = $urandom_range (8);
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r_row = $urandom_range (1<<ROW_BITS);
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r_col = $urandom_range (1<<COL_BITS);
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r_data = {$urandom,$urandom,$urandom,$urandom,$urandom,$urandom,$urandom,$urandom};
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activate (r_bank, r_row);
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nop (trcd);
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write (r_bank, r_col, 0, 0, 0, r_data);
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nop (wl + bl/2 + twtr);
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read (r_bank, r_col, 0, 0);
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nop (rl + bl/2);
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precharge (r_bank, 0);
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nop (trp);
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end
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nop (20);
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/*
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trcd);
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$display ("READ (BL4) to WRITE (BL4)");
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read (0, 0, 0, 0);
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nop (rl + tccd/2 + 1 - wl);
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write (0, 0, 0, 0, 0, 10);
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$display ("Consecutive WRITE (BL8) to WRITE (BL8)");
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nop (tccd - 1);
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write (0, 0, 0, 1, 0, 20);
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nop (tccd - 1);
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write (0, 0, 0, 1, 0, 30);
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$display ("Consecutive WRITE (BL4) to WRITE (BL4)");
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nop (tccd - 1);
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write (0, 0, 0, 0, 0, 40);
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nop (tccd - 1);
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write (0, 0, 0, 0, 0, 50);
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$display ("WRITE (BL4 on the fly) to READ (BL4 on the fly)");
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nop (cwl + 3 + twtr);
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read_verify (0, 0, 0, 0, 0, 50);
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nop (rl + tccd/2 + 1 - wl);
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$display ("READ (BL4) to WRITE (BL8)");
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write (0, 0, 0, 1, 0, 10);
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nop (cwl + 3 + twtr);
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$display ("WRITE (BL8) to READ (BL4)");
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read_verify (0, 0, 1, 0, 0, 10);
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nop (al + trtp + trp);
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$display ("tRRD Timing");
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activate (0, 0);
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nop (trrd - 1);
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activate (1, 0);
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nop (trrd - 1);
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activate (2, 0);
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nop (trrd - 1);
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activate (3, 0);
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nop (trcd - 1);
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$display ("Consecutive Writes");
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write (0, 0, 0, 1, 0, d0);
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nop (tccd - 1);
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write (1, 0, 0, 1, 0, d1);
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nop (tccd - 1);
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write (2, 0, 0, 1, 0, d2);
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nop (tccd - 1);
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write (3, 0, 0, 1, 0, d3);
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nop (wl + bl/2 + twtr);
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$display ("Consecutive Reads");
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read_verify (0, 0, 0, 1, 0, d0);
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nop (tccd - 1);
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read_verify (1, 0, 0, 1, 0, d1);
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nop (tccd - 1);
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read_verify (2, 0, 0, 1, 0, d2);
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nop (tccd - 1);
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read_verify (3, 0, 0, 1, 0, d3);
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nop (rl + bl/2);
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$display ("Non Consecutive Writes");
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write (0, 0, 0, 1, 0, d0);
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nop (tccd);
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write (1, 0, 0, 1, 0, d1);
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nop (tccd);
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write (2, 0, 0, 1, 0, d2);
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nop (tccd);
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write (3, 0, 0, 1, 0, d3);
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nop (wl + bl/2 + twtr);
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$display ("Non Consecutive Reads");
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read_verify (0, 0, 1, 1, 0, d0);
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nop (tccd);
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read_verify (1, 0, 1, 1, 0, d1);
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nop (tccd);
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read_verify (2, 0, 1, 1, 0, d2);
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nop (tccd);
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read_verify (3, 0, 1, 1, 0, d3);
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nop (max(rl + bl/2, al + trtp + trp - 1));
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// POWER DOWN SECTION
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odt_out <= 1'b0;
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odt_out <= #(50*tck) 1'b1;
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odt_out <= #((50 + BL_MAX)*tck) 1'b0;
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refresh;
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power_down (trfc);
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nop (txp);
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self_refresh (trfc);
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nop (txsdll);
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$display ("Power-Down Entry after WRITE /w AP (WRA)");
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load_mode (0, {14'b0_0_000_0_0_000_1_0_10} | mr_wr<<9 | mr_cl<<2); // Mode Register with Burst Chop
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nop (tmod-1);
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trcd-1);
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write (0, 0, 1, 0, 0, 10);
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nop (wl + bl/2 + twr-1);
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power_down (tcke-1);
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nop (txpdll);
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$display ("refresh to power down re-entry");
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refresh;
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power_down (tcke-1);
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nop (trfc-tcke);
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power_down (tcke-1);
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nop (txp);
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$display ("Power-Down Exit to Refresh to Power-Down Entry");
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refresh;
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nop (txpdll-txp-1);
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power_down (tcke-1);
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nop (trfc-txp);
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$display ("Change Frequency during Precharge Power-down");
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original_tck <= tck;
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pd_change_period (TCK_MAX);
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nop (tcke + 1);
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$display ("Change Frequency during Self Refresh");
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sr_change_period (original_tck);
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nop (txsdll);
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// multipurpose register section
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// pre-defined pattern
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load_mode (3, 14'b00000000000100);
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nop (tmod);
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read (0, 0, 0, 1);
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nop (rl + bl/2 + trtp);
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load_mode (3, 14'b00000000000000);
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nop (tmod);
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// self refresh with ck off
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cke <= 1'b0;
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self_refresh (tcksre);
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assign ck = 0;
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# (trfc*tck);
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deassign ck;
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ck <= 1'b1;
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# ((tcksrx + 0.5)*tck);
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nop (txsdll + 1);
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// write levelization section
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load_mode (2, {14'b00000000_000_000} | mr_cwl<<3); // Extended Mode Register 2 with DCC Disable
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nop (tmrd - 1);
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load_mode (1, 14'b00000010010110);
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nop (tmod);
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odt_out <= 1'b1;
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nop (TWLDQSEN - tmod);
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dqs_en <= 1'b1;
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dqs_out <= {DQS_BITS{1'b0}};
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nop (TWLMRD - TWLDQSEN);
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dqs_out <= #(TWLH + 1) {DQS_BITS{1'b1}};
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dqs_out <= #(TWLH + tck/2 + 1) {DQS_BITS{1'b0}};
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nop (16);
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dqs_out <= #(TWLH + tck/2 + 1) {DQS_BITS{1'b1}};
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dqs_out <= #(TWLH + tck + 1) {DQS_BITS{1'b0}};
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odt_out <= 1'b0;
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nop (wl - 1); // ODTLoff + tAOF
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load_mode (1, 14'b00000000010110);
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dqs_en <= 1'b0;
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nop (tmod);
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power_up;
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nop (txp);
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// INITIALIZE SECTION
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zq_calibration (1); // perform Long ZQ Calibration
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load_mode (3, 14'b00000000000000); // Extended Mode Register (3)
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nop (tmrd - 1);
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load_mode (2, {14'b00001000_000_000} | mr_cwl<<3); // Extended Mode Register 2 with DCC Disable
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nop (tmrd - 1);
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load_mode (1, 14'b0000010110); // Extended Mode Register with DLL Enable, AL=CL-1
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nop (tmrd - 1);
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load_mode (0, {14'b0_0_000_1_0_000_1_0_01} | mr_wr<<9 | mr_cl<<2); // Mode Register with DLL Reset
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nop (tdllk);
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odt_out <= 1'b1;
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trcd);
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read (0, 1, 1, 1);
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nop (rl + bl/2 + trtp + trp);
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`ifdef TRUEBL4
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// true BL4 section
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odt_out <= 1'b0;
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nop (wl - 1); // ODTLoff + tAOF
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load_mode (1, 14'b00000000000110); // Extended Mode Register with DLL Enable, AL=0
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nop (tmrd - 1);
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load_mode (0, {14'b0_0_000_0_0_000_0_0_11} | mr_wr<<9 | mr_cl<<2); // Mode Register with true BL4
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nop (tmod - 1);
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odt_out <= 1'b1;
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$display ("tRRD Timing in True BL4 Mode");
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activate (0, 0);
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nop (trrd_dg - 1);
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activate (2, 0);
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nop (max(trcd - trrd_dg - 1, trcd - tccd_dg - 1));
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$display ("Consecutive True BL4 Writes");
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write (0, 0, 0, 0, 0, d0);
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nop (tccd_dg - 1);
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write (2, 0, 0, 0, 0, d1);
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nop (tccd_dg - 1);
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write (0, 0, 0, 0, 0, d2);
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nop (tccd_dg - 1);
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write (2, 0, 0, 0, 0, d3);
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nop (wl + bl/2 + twtr_dg);
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$display ("Consecutive True BL4 Reads");
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read_verify (0, 0, 0, 0, 0, d2);
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nop (tccd_dg - 1);
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read_verify (2, 0, 0, 0, 0, d3);
|
||
|
|
nop (rl + bl/2);
|
||
|
|
|
||
|
|
$display ("Non Consecutive True BL4 Writes");
|
||
|
|
write (0, 0, 0, 0, 0, d0);
|
||
|
|
nop (tccd_dg);
|
||
|
|
write (2, 0, 0, 0, 0, d1);
|
||
|
|
nop (tccd_dg);
|
||
|
|
write (0, 0, 0, 0, 0, d2);
|
||
|
|
nop (tccd_dg);
|
||
|
|
write (2, 0, 0, 0, 0, d3);
|
||
|
|
nop (wl + bl/2 + twtr_dg);
|
||
|
|
|
||
|
|
$display ("Non Consecutive True BL4 Reads");
|
||
|
|
read_verify (0, 0, 0, 0, 0, d2);
|
||
|
|
nop (tccd_dg);
|
||
|
|
read_verify (2, 0, 0, 0, 0, d3);
|
||
|
|
nop (rl + tccd_dg/2 + 2 - wl - 1);
|
||
|
|
|
||
|
|
$display ("True BL4 Write to Read (Same Group)");
|
||
|
|
write (0, 0, 0, 0, 0, d0);
|
||
|
|
nop (wl + bl/2 + twtr - 1);
|
||
|
|
read_verify (0, 0, 0, 0, 0, d0);
|
||
|
|
nop (rl + tccd_dg/2 + 2 - wl - 1);
|
||
|
|
|
||
|
|
$display ("True BL4 Write to Read (Different Group)");
|
||
|
|
write (2, 0, 0, 0, 0, d1);
|
||
|
|
nop (wl + bl/2 + twtr_dg - 1);
|
||
|
|
read_verify (0, 0, 0, 0, 0, d0);
|
||
|
|
nop (rl + bl/2);
|
||
|
|
`endif
|
||
|
|
*/
|
||
|
|
|
||
|
|
test_done;
|
||
|
|
end
|