242 lines
7.2 KiB
Python
242 lines
7.2 KiB
Python
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#!/usr/bin/env python3
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import sys
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.soc.integration.builder import *
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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_io = [
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("clk", 0, Pins("X")),
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("rst", 0, Pins("X")),
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]
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "", _io)
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class LiteDRAMCoreSim(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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# sdram parameters
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sdram_aw = 24
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sdram_dw = 128
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# sdram bist
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sdram_generator_port = LiteDRAMNativePort("both", sdram_aw, sdram_dw, id=0)
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self.submodules.sdram_generator = _LiteDRAMBISTGenerator(sdram_generator_port)
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sdram_checker_port = LiteDRAMNativePort("both", sdram_aw, sdram_dw, id=1)
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self.submodules.sdram_checker = _LiteDRAMBISTChecker(sdram_checker_port)
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# micron model
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ddram_a = Signal(14)
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ddram_ba = Signal(3)
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ddram_ras_n = Signal()
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ddram_cas_n = Signal()
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ddram_we_n = Signal()
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ddram_cs_n = Signal()
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ddram_dm = Signal(2)
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ddram_dq = Signal(16)
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ddram_dqs_p = Signal(2)
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ddram_dqs_n = Signal(2)
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ddram_clk_p = Signal()
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ddram_clk_n = Signal()
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ddram_cke = Signal()
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ddram_odt = Signal()
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ddram_reset_n = Signal()
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self.specials += Instance("ddr3",
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i_rst_n=ddram_reset_n,
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i_ck=ddram_clk_p,
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i_ck_n=ddram_clk_n,
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i_cke=ddram_cke,
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i_cs_n=ddram_cs_n,
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i_ras_n=ddram_ras_n,
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i_cas_n=ddram_cas_n,
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i_we_n=ddram_we_n,
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io_dm_tdqs=ddram_dm,
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i_ba=ddram_ba,
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i_addr=ddram_a,
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io_dq=ddram_dq,
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io_dqs=ddram_dqs_p,
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io_dqs_n=ddram_dqs_n,
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#o_tdqs_n=,
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i_odt=ddram_odt
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)
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# LiteDRAM standalone core instance
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init_done = Signal()
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init_error = Signal()
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self.specials += Instance("litedram_core",
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# clk / reset input
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i_clk=platform.request("clk"),
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i_rst=platform.request("rst"),
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# dram pins
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o_ddram_a=ddram_a,
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o_ddram_ba=ddram_ba,
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o_ddram_ras_n=ddram_ras_n,
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o_ddram_cas_n=ddram_cas_n,
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o_ddram_we_n=ddram_we_n,
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o_ddram_cs_n=ddram_cs_n,
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o_ddram_dm=ddram_dm,
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io_ddram_dq=ddram_dq,
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o_ddram_dqs_p=ddram_dqs_p,
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o_ddram_dqs_n=ddram_dqs_n,
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o_ddram_clk_p=ddram_clk_p,
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o_ddram_clk_n=ddram_clk_n,
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o_ddram_cke=ddram_cke,
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o_ddram_odt=ddram_odt,
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o_ddram_reset_n=ddram_reset_n,
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# dram init
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o_init_done=init_done,
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o_init_error=init_error,
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# user clk / reset
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o_user_clk=self.cd_sys.clk,
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o_user_rst=self.cd_sys.rst,
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# user port 0
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# cmd
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i_user_port0_cmd_valid=sdram_generator_port.cmd.valid,
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o_user_port0_cmd_ready=sdram_generator_port.cmd.ready,
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i_user_port0_cmd_we=sdram_generator_port.cmd.we,
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i_user_port0_cmd_addr=sdram_generator_port.cmd.addr,
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# wdata
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i_user_port0_wdata_valid=sdram_generator_port.wdata.valid,
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o_user_port0_wdata_ready=sdram_generator_port.wdata.ready,
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i_user_port0_wdata_we=sdram_generator_port.wdata.we,
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i_user_port0_wdata_data=sdram_generator_port.wdata.data,
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# rdata
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o_user_port0_rdata_valid=sdram_generator_port.rdata.valid,
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i_user_port0_rdata_ready=sdram_generator_port.rdata.ready,
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o_user_port0_rdata_data=sdram_generator_port.rdata.data,
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# user port 1
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# cmd
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i_user_port1_cmd_valid=sdram_checker_port.cmd.valid,
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o_user_port1_cmd_ready=sdram_checker_port.cmd.ready,
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i_user_port1_cmd_we=sdram_checker_port.cmd.we,
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i_user_port1_cmd_addr=sdram_checker_port.cmd.addr,
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# wdata
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i_user_port1_wdata_valid=sdram_checker_port.wdata.valid,
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o_user_port1_wdata_ready=sdram_checker_port.wdata.ready,
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i_user_port1_wdata_we=sdram_checker_port.wdata.we,
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i_user_port1_wdata_data=sdram_checker_port.wdata.data,
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# rdata
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o_user_port1_rdata_valid=sdram_checker_port.rdata.valid,
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i_user_port1_rdata_ready=sdram_checker_port.rdata.ready,
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o_user_port1_rdata_data=sdram_checker_port.rdata.data
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)
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# test
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self.comb += [
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self.sdram_generator.base.eq(0x00000000),
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self.sdram_generator.length.eq(0x00000100),
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self.sdram_checker.base.eq(0x00000000),
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self.sdram_checker.length.eq(0x00000100),
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(init_done,
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NextState("GENERATOR_START")
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)
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)
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fsm.act("GENERATOR_START",
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self.sdram_generator.start.eq(1),
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NextState("GENERATOR_WAIT")
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)
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fsm.act("GENERATOR_WAIT",
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If(self.sdram_generator.done,
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NextState("CHECKER_START")
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)
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)
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fsm.act("CHECKER_START",
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self.sdram_checker.start.eq(1),
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NextState("CHECKER_WAIT")
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)
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fsm.act("CHECKER_WAIT",
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If(self.sdram_checker.done,
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NextState("DONE")
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)
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)
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fsm.act("DONE")
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def generate_core():
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os.system("cd .. && python3 litedram_gen.py sim/sim_config.py")
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def generate_top():
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platform = Platform()
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soc = LiteDRAMCoreSim(platform)
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platform.build(soc, build_dir="./", run=False)
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def generate_top_tb():
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f = open("top_tb.v", "w")
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f.write("""
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`timescale 1ns/1ps
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module top_tb();
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reg clk;
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initial clk = 1'b1;
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always #5 clk = ~clk;
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top dut (
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.clk(clk),
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.rst(0)
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);
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endmodule""")
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f.close()
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def copy_core():
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os.system("cp ../build/gateware/litedram_core.v ./")
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os.system("cp ../build/gateware/litedram_core.init ./")
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def run_sim(gui=False):
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os.system("rm -rf xsim.dir")
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if sys.platform == "win32":
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call_cmd = "call "
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else:
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call_cmd = ""
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os.system(call_cmd + "xvlog glbl.v")
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os.system(call_cmd + "xvlog micron/4096Mb_ddr3_parameters.vh -sv")
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os.system(call_cmd + "xvlog micron/ddr3.v -sv")
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os.system(call_cmd + "xvlog litedram_core.v -sv")
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os.system(call_cmd + "xvlog top.v -sv")
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os.system(call_cmd + "xvlog top_tb.v -sv ")
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os.system(call_cmd + "xelab -debug typical top_tb glbl -s top_tb_sim -L unisims_ver -L unimacro_ver -L SIMPRIM_VER -L secureip -L $xsimdir/xil_defaultlib -timescale 1ns/1ps")
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if gui:
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os.system(call_cmd + "xsim top_tb_sim -gui")
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else:
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os.system(call_cmd + "xsim top_tb_sim -runall")
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def main():
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generate_core()
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generate_top()
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generate_top_tb()
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copy_core()
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run_sim(gui="gui" in sys.argv[1:])
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if __name__ == "__main__":
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main()
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