49 lines
1.4 KiB
Python
49 lines
1.4 KiB
Python
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from litex.gen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMPort
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from litedram.frontend.crossbar import LiteDRAMConverter
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from test.common import DRAMMemory
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class TB(Module):
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def __init__(self):
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self.user_port = LiteDRAMPort(aw=32, dw=32)
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self.internal_port = LiteDRAMPort(aw=32, dw=64)
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self.submodules.converter = LiteDRAMConverter(self.user_port, self.internal_port)
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self.memory = DRAMMemory(64, 128)
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def main_generator(dut):
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for i in range(8):
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yield
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# write
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for i in range(8):
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yield dut.user_port.cmd.valid.eq(1)
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yield dut.user_port.cmd.we.eq(1)
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yield dut.user_port.cmd.adr.eq(i)
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yield
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while (yield dut.user_port.cmd.ready) == 0:
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yield
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yield dut.user_port.cmd.valid.eq(0)
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yield
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yield dut.user_port.wdata.valid.eq(1)
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if i%2:
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yield dut.user_port.wdata.data.eq(0x01234567)
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else:
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yield dut.user_port.wdata.data.eq(0x89abcdef)
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yield
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while (yield dut.user_port.wdata.ready) == 0:
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yield
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yield dut.user_port.wdata.valid.eq(0)
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yield
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if __name__ == "__main__":
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tb = TB()
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generators = {
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"sys" : [main_generator(tb),
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tb.memory.write_generator(tb.internal_port)]
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}
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clocks = {"sys": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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