73 lines
2.2 KiB
Python
73 lines
2.2 KiB
Python
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import unittest
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import random
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from migen import *
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.axi import *
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from litex.gen.sim import *
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def main_generator(axi_port, dram_port, dut):
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prng = random.Random(42)
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# axi_port always accepting wresps/rdatas
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yield axi_port.b.ready.eq(1)
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yield axi_port.r.ready.eq(1)
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yield
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# test writes
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for i in range(16):
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# write command
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yield axi_port.aw.valid.eq(1)
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yield axi_port.aw.addr.eq(i)
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while (yield dram_port.cmd.ready) == 0:
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if prng.randrange(100) < 20:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield axi_port.aw.valid.eq(0)
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yield dram_port.cmd.ready.eq(0)
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yield
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# write data
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yield axi_port.w.valid.eq(1)
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yield axi_port.w.data.eq(i)
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while (yield dram_port.wdata.ready) == 0:
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if prng.randrange(100) < 20:
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yield dram_port.wdata.ready.eq(1)
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yield
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if (yield axi_port.w.ready) == 1:
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yield axi_port.w.valid.eq(0)
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yield axi_port.aw.valid.eq(0)
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yield dram_port.wdata.ready.eq(0)
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yield
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# test reads
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for i in range(16):
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# read command
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yield axi_port.ar.valid.eq(1)
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yield axi_port.ar.addr.eq(i)
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while (yield dram_port.cmd.ready) == 0:
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if prng.randrange(100) < 20:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield axi_port.ar.valid.eq(0)
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yield dram_port.cmd.ready.eq(0)
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yield
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# read data
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yield dram_port.rdata.valid.eq(1)
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yield dram_port.rdata.data.eq(i)
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while (yield dram_port.rdata.valid) == 0:
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if prng.randrange(100) < 20:
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yield dram_port.rdata.valid.eq(1)
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yield
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yield axi_port.ar.valid.eq(0)
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yield dram_port.rdata.valid.eq(0)
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yield
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for i in range(128):
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yield
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class TestAXI(unittest.TestCase):
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def test(self):
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axi_port = LiteDRAMAXIPort(32, 24, 32)
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dram_port = LiteDRAMNativePort("both", 24, 32)
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dut = LiteDRAMAXI2Native(axi_port, dram_port)
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run_simulation(dut, main_generator(axi_port, dram_port, dut), vcd_name="axi.vcd")
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