21 lines
575 B
Python
21 lines
575 B
Python
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from migen.fhdl.std import *
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from migen.sim.generic import run_simulation
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from litedram.common import *
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from litedram.module import MT48LC4M16
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from litedram.core.bankmachine import LiteDRAMBankMachine
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from test.common import *
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class TB(Module):
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def __init__(self):
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sdram_module = MT48LC4M16(100)
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self.submodules.bankmachine = LiteDRAMBankMachine(sdram_module, 16)
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def gen_simulation(self, selfp):
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for i in range(100):
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yield
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)
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