54 lines
1.7 KiB
Python
54 lines
1.7 KiB
Python
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from litex.gen import *
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class DRAMMemory:
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def __init__(self, width, depth, init=[]):
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self.width = width
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self.depth = depth
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self.mem = []
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for d in init:
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self.mem.append(d)
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for _ in range(depth-len(init)):
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self.mem.append(0)
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@passive
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def read_generator(self, dram_port):
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address = 0
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pending = 0
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while True:
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yield dram_port.cmd.ready.eq(0)
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yield dram_port.rdata.valid.eq(0)
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if pending:
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yield dram_port.rdata.valid.eq(1)
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yield dram_port.rdata.data.eq(self.mem[address%self.depth])
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yield
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yield dram_port.rdata.valid.eq(0)
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yield dram_port.rdata.data.eq(0)
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pending = 0
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elif (yield dram_port.cmd.valid):
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pending = not (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.adr)
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yield
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yield dram_port.cmd.ready.eq(1)
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yield
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@passive
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def write_generator(self, dram_port):
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address = 0
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pending = 0
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while True:
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yield dram_port.cmd.ready.eq(0)
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yield dram_port.wdata.ready.eq(0)
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if pending:
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yield dram_port.wdata.ready.eq(1)
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yield
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self.mem[address%self.depth] = (yield dram_port.wdata.data) # TODO manage we
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yield dram_port.wdata.ready.eq(0)
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yield
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pending = 0
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elif (yield dram_port.cmd.valid):
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pending = yield dram_port.cmd.we
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address = (yield dram_port.cmd.adr)
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yield
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yield dram_port.cmd.ready.eq(1)
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yield
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