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litedram/test/benchmarks.yml

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test: load benchmark configurations from YAML file
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{
"test_0": {
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
test: add random address generation in benchmarks
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"bist_random": true
test: add handling of alternating write/read to benchmark runner
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}
test: load benchmark configurations from YAML file
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},
"test_1": {
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
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"bist_length": 1,
test: add handling of alternating write/read to benchmark runner
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"bist_random": false
}
test: load benchmark configurations from YAML file
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},
"test_2": {
test: add random address generation in benchmarks
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": true
}
},
"test_3": {
"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
},
"test_4": {
"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": true
}
},
"test_5": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
test: load benchmark configurations from YAML file
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},
test: add random address generation in benchmarks
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"test_6": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
test: load benchmark configurations from YAML file
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},
test: add random address generation in benchmarks
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"test_7": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
test: load benchmark configurations from YAML file
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},
test: add random address generation in benchmarks
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"test_8": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
test: load benchmark configurations from YAML file
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},
test: add random address generation in benchmarks
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"test_9": {
"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
"bist_random": true
}
},
"test_10": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
test: load benchmark configurations from YAML file
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},
test: add random address generation in benchmarks
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"test_11": {
"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": true
}
},
"test_12": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
},
test: add random address generation in benchmarks
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"test_13": {
"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": true
}
},
"test_14": {
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
test: add read/write latency benchmarks
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},
test: add random address generation in benchmarks
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"test_15": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
test: add read/write latency benchmarks
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},
test: add random address generation in benchmarks
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"test_16": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
test: add read/write latency benchmarks
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},
test: add random address generation in benchmarks
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"test_17": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
},
test: add random address generation in benchmarks
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"test_18": {
"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
"bist_random": true
}
},
"test_19": {
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_20": {
"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": true
}
},
"test_21": {
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_22": {
"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": true
}
},
"test_23": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_24": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
},
test: add random address generation in benchmarks
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"test_25": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_26": {
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_27": {
"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
"bist_random": true
}
},
"test_28": {
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_29": {
"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": true
}
},
"test_30": {
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_31": {
"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": true
}
},
"test_32": {
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_33": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_34": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 1024,
"bist_random": false
}
test: add new benchmark configuratiosns to example configuration file
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},
test: add random address generation in benchmarks
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"test_35": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"bist_length": 8192,
"bist_random": false
}
},
test: add random address generation in benchmarks
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"test_36": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
},
test: add random address generation in benchmarks
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"test_37": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT41K128M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
},
test: add random address generation in benchmarks
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"test_38": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
},
test: add random address generation in benchmarks
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"test_39": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT46V32M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
},
test: add random address generation in benchmarks
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"test_40": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
},
test: add random address generation in benchmarks
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"test_41": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT47H64M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
},
test: add random address generation in benchmarks
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"test_42": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": true,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
test: add read/write latency benchmarks
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},
test: add random address generation in benchmarks
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"test_43": {
test: add handling of alternating write/read to benchmark runner
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"sdram_module": "MT48LC16M16",
"sdram_data_width": 32,
"bist_alternating": false,
"access_pattern": {
"pattern_file": "access_pattern.csv"
}
}
test: load benchmark configurations from YAML file
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}