2019-06-23 17:56:50 -04:00
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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2018-09-15 17:36:12 -04:00
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import unittest
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import random
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from migen import *
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2018-09-15 18:39:33 -04:00
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from litedram.common import *
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2018-09-15 17:36:12 -04:00
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from litedram.frontend.ecc import *
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from litex.gen.sim import *
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class TestECC(unittest.TestCase):
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2018-09-15 18:39:33 -04:00
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def test_ecc_wrapper(self):
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# 32 bits + 8 bits ecc
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port_from = LiteDRAMNativePort("both", 24, 32*8)
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port_to = LiteDRAMNativePort("both", 24, 40*8)
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ecc = LiteDRAMNativePortECC(port_from, port_to)
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# 64 bits + 8 bits ecc
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port_from = LiteDRAMNativePort("both", 24, 64*8)
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port_to = LiteDRAMNativePort("both", 24, 72*8)
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ecc = LiteDRAMNativePortECC(port_from, port_to)
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