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litedram/test/reference/sdr_init.h

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test: add test_init with sdr/ddr3/ddr4 references
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#ifndef __GENERATED_SDRAM_PHY_H
#define __GENERATED_SDRAM_PHY_H
#include <hw/common.h>
#include <generated/csr.h>
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#define DFII_CONTROL_SEL 0x01
#define DFII_CONTROL_CKE 0x02
#define DFII_CONTROL_ODT 0x04
#define DFII_CONTROL_RESET_N 0x08
#define DFII_COMMAND_CS 0x01
#define DFII_COMMAND_WE 0x02
#define DFII_COMMAND_CAS 0x04
#define DFII_COMMAND_RAS 0x08
#define DFII_COMMAND_WRDATA 0x10
#define DFII_COMMAND_RDDATA 0x20
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#define SDRAM_PHY_GENSDRPHY
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#define SDRAM_PHY_XDR 1
#define SDRAM_PHY_DATABITS 16
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#define SDRAM_PHY_PHASES 1
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#define SDRAM_PHY_RDPHASE 0
#define SDRAM_PHY_WRPHASE 0
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static void cdelay(int i);
__attribute__((unused)) static void command_p0(int cmd)
{
sdram_dfii_pi0_command_write(cmd);
sdram_dfii_pi0_command_issue_write(1);
}
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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const unsigned long sdram_dfii_pix_wrdata_addr[SDRAM_PHY_PHASES] = {
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CSR_SDRAM_DFII_PI0_WRDATA_ADDR
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};
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const unsigned long sdram_dfii_pix_rddata_addr[SDRAM_PHY_PHASES] = {
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CSR_SDRAM_DFII_PI0_RDDATA_ADDR
test: add test_init with sdr/ddr3/ddr4 references
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};
static void init_sequence(void)
{
/* Bring CKE high */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
cdelay(20000);
/* Precharge All */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register / Reset DLL, CL=2, BL=1 */
sdram_dfii_pi0_address_write(0x120);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* Precharge All */
sdram_dfii_pi0_address_write(0x400);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Auto Refresh */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4);
/* Auto Refresh */
sdram_dfii_pi0_address_write(0x0);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4);
/* Load Mode Register / CL=2, BL=1 */
sdram_dfii_pi0_address_write(0x20);
sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
#endif