74 lines
2.2 KiB
Python
74 lines
2.2 KiB
Python
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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import random
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from migen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMNativeWritePort
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from litedram.common import LiteDRAMNativeReadPort
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from litedram.frontend.fifo import LiteDRAMFIFO
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from test.common import *
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class FIFODUT(Module):
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def __init__(self):
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# ports
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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# fifo
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self.submodules.fifo = LiteDRAMFIFO(
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data_width = 32,
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depth = 64,
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base = 0,
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write_port = self.write_port,
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read_port = self.read_port,
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read_threshold = 8,
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write_threshold = 64-8
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)
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# memory
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self.memory = DRAMMemory(32, 256)
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class TestFIFO(unittest.TestCase):
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def test_fifo(self):
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def generator(dut, valid_random=90):
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prng = random.Random(42)
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for i in range(128 + 8):
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while prng.randrange(100) < valid_random:
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yield
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yield dut.fifo.sink.valid.eq(1)
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yield dut.fifo.sink.data.eq(i)
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yield
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while (yield dut.fifo.sink.ready) != 1:
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yield
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yield dut.fifo.sink.valid.eq(0)
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def checker(dut, ready_random=90):
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prng = random.Random(42)
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for i in range(128):
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yield dut.fifo.source.ready.eq(0)
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yield
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while (yield dut.fifo.source.valid) != 1:
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yield
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while prng.randrange(100) < ready_random:
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yield
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yield dut.fifo.source.ready.eq(1)
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self.assertEqual((yield dut.fifo.source.data), i)
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yield
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dut = FIFODUT()
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generators = [
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generator(dut),
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checker(dut),
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dut.memory.write_handler(dut.write_port),
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dut.memory.read_handler(dut.read_port)
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]
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run_simulation(dut, generators)
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