98 lines
2.9 KiB
Python
98 lines
2.9 KiB
Python
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from litex.gen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import PhySettings, LiteDRAMPort
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from litedram.core import *
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from litedram.modules import SDRAMModule
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from litedram.frontend.crossbar import LiteDRAMCrossbar
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from litedram.frontend.bist import LiteDRAMBISTGenerator
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from litedram.frontend.bist import LiteDRAMBISTChecker
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from litedram.phy.model import SDRAMPHYModel
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class SimModule(SDRAMModule):
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# geometry
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nbanks = 4
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nrows = 2048
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ncols = 4
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# timings
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tRP = 1
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tRCD = 1
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tWR = 1
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tWTR = 1
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tREFI = 1
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tRFC = 1
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class TB(Module):
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def __init__(self):
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sdram_module = SimModule(1000, "1:1")
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phy_settings = PhySettings(
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memtype="SDR",
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dfi_databits=1*16,
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nphases=1,
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rdphase=0,
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wrphase=0,
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rdcmdphase=0,
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wrcmdphase=0,
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cl=2,
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read_latency=4,
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write_latency=0
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)
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self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
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self.submodules.controller = LiteDRAMController(
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phy_settings,
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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ControllerSettings(with_refresh=False))
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self.comb += self.controller.dfi.connect(self.sdrphy.dfi)
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self.submodules.crossbar = LiteDRAMCrossbar(self.controller.interface,
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self.controller.nrowbits)
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self.write_port = self.crossbar.get_port(cd="write")
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self.read_port = self.crossbar.get_port(cd="read")
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, cd="write")
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port, cd="read")
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def main_generator(dut):
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for i in range(100):
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yield
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# write
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yield dut.generator.base.storage.eq(16)
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yield dut.generator.length.storage.eq(16)
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for i in range(32):
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yield
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yield dut.generator.shoot.re.eq(1)
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yield
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yield dut.generator.shoot.re.eq(0)
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for i in range(32):
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yield
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while((yield dut.generator.done.status) == 0):
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yield
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# read
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(16)
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for i in range(32):
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yield
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yield dut.checker.shoot.re.eq(1)
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yield
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yield dut.checker.shoot.re.eq(0)
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for i in range(32):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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# check
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print("errors {:d}".format((yield dut.checker.error_count.status)))
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yield
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if __name__ == "__main__":
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tb = TB()
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generators = {
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"sys" : [main_generator(tb)]
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}
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clocks = {"sys": 10,
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"write": 12,
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"read": 8}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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