remove minicon
This commit is contained in:
Florent Kermarrec
parent
319ecdc986
commit
0051f368cc
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from litedram.minicon.core import Minicon
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from functools import reduce
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from operator import or_
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from litex.gen import *
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from litex.gen.genlib.fsm import FSM, NextState
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from litex.gen.genlib.misc import WaitTimer
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from litedram.phy import dfi as dfibus
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from litex.soc.interconnect import wishbone
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class _AddressSlicer:
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def __init__(self, colbits, bankbits, rowbits, address_align):
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self.colbits = colbits
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self.bankbits = bankbits
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self.rowbits = rowbits
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self.address_align = address_align
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self.addressbits = colbits - address_align + bankbits + rowbits
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def row(self, address):
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split = self.bankbits + self.colbits - self.address_align
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if isinstance(address, int):
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return address >> split
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else:
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return address[split:self.addressbits]
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def bank(self, address):
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split = self.colbits - self.address_align
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if isinstance(address, int):
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return (address & (2**(split + self.bankbits) - 1)) >> split
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else:
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return address[split:split+self.bankbits]
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def col(self, address):
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split = self.colbits - self.address_align
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if isinstance(address, int):
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return (address & (2**split - 1)) << self.address_align
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else:
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return Cat(Replicate(0, self.address_align), address[:split])
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@ResetInserter()
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@CEInserter()
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class _Bank(Module):
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def __init__(self, geom_settings):
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self.open = Signal()
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self.row = Signal(geom_settings.rowbits)
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self.idle = Signal(reset=1)
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self.hit = Signal()
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# # #
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row = Signal(geom_settings.rowbits)
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self.sync += \
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If(self.open,
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self.idle.eq(0),
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row.eq(self.row)
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)
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self.comb += self.hit.eq(~self.idle & (self.row == row))
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class Minicon(Module):
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def __init__(self, phy_settings, geom_settings, timing_settings):
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if phy_settings.memtype in ["SDR"]:
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burst_length = phy_settings.nphases*1 # command multiplication*SDR
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elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
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burst_length = phy_settings.nphases*2 # command multiplication*DDR
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burst_width = phy_settings.dfi_databits*phy_settings.nphases
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address_align = log2_int(burst_length)
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# # #
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self.dfi = dfi = dfibus.Interface(geom_settings.addressbits,
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geom_settings.bankbits,
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phy_settings.dfi_databits,
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phy_settings.nphases)
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self.bus = bus = wishbone.Interface(burst_width)
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rdphase = phy_settings.rdphase
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wrphase = phy_settings.wrphase
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precharge_all = Signal()
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activate = Signal()
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refresh = Signal()
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write = Signal()
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read = Signal()
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# Compute current column, bank and row from wishbone address
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slicer = _AddressSlicer(geom_settings.colbits,
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geom_settings.bankbits,
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geom_settings.rowbits,
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address_align)
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# Manage banks
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bank_idle = Signal()
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bank_hit = Signal()
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banks = []
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for i in range(2**geom_settings.bankbits):
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bank = _Bank(geom_settings)
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self.comb += [
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bank.open.eq(activate),
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bank.reset.eq(precharge_all),
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bank.row.eq(slicer.row(bus.adr))
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]
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banks.append(bank)
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self.submodules += banks
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cases = {}
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for i, bank in enumerate(banks):
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cases[i] = [bank.ce.eq(1)]
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self.comb += Case(slicer.bank(bus.adr), cases)
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self.comb += [
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bank_hit.eq(reduce(or_, [bank.hit & bank.ce for bank in banks])),
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bank_idle.eq(reduce(or_, [bank.idle & bank.ce for bank in banks])),
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]
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# Timings
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write2precharge_timer = WaitTimer(2 + timing_settings.tWR - 1)
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self.submodules += write2precharge_timer
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self.comb += write2precharge_timer.wait.eq(~write)
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refresh_timer = WaitTimer(timing_settings.tREFI)
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self.submodules += refresh_timer
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self.comb += refresh_timer.wait.eq(~refresh)
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# Main FSM
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self.submodules.fsm = fsm = FSM()
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fsm.act("IDLE",
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If(refresh_timer.done,
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NextState("PRECHARGE-ALL")
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).Elif(bus.stb & bus.cyc,
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If(bank_hit,
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If(bus.we,
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NextState("WRITE")
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).Else(
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NextState("READ")
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)
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).Elif(~bank_idle,
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If(write2precharge_timer.done,
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NextState("PRECHARGE")
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)
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).Else(
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NextState("ACTIVATE")
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)
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)
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)
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fsm.act("READ",
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read.eq(1),
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dfi.phases[rdphase].ras_n.eq(1),
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dfi.phases[rdphase].cas_n.eq(0),
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dfi.phases[rdphase].we_n.eq(1),
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dfi.phases[rdphase].rddata_en.eq(1),
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NextState("WAIT-READ-DONE"),
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)
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fsm.act("WAIT-READ-DONE",
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If(dfi.phases[rdphase].rddata_valid,
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bus.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("WRITE",
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write.eq(1),
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dfi.phases[wrphase].ras_n.eq(1),
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dfi.phases[wrphase].cas_n.eq(0),
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dfi.phases[wrphase].we_n.eq(0),
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dfi.phases[wrphase].wrdata_en.eq(1),
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NextState("WRITE-LATENCY")
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)
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fsm.act("WRITE-ACK",
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bus.ack.eq(1),
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NextState("IDLE")
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)
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fsm.act("PRECHARGE-ALL",
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precharge_all.eq(1),
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dfi.phases[rdphase].ras_n.eq(0),
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dfi.phases[rdphase].cas_n.eq(1),
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dfi.phases[rdphase].we_n.eq(0),
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NextState("PRE-REFRESH")
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)
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fsm.act("PRECHARGE",
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# do no reset bank since we are going to re-open it
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dfi.phases[0].ras_n.eq(0),
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dfi.phases[0].cas_n.eq(1),
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dfi.phases[0].we_n.eq(0),
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NextState("TRP")
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)
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fsm.act("ACTIVATE",
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activate.eq(1),
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dfi.phases[0].ras_n.eq(0),
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dfi.phases[0].cas_n.eq(1),
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dfi.phases[0].we_n.eq(1),
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NextState("TRCD"),
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)
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fsm.act("REFRESH",
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refresh.eq(1),
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dfi.phases[rdphase].ras_n.eq(0),
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dfi.phases[rdphase].cas_n.eq(0),
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dfi.phases[rdphase].we_n.eq(1),
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NextState("POST-REFRESH")
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)
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fsm.delayed_enter("WRITE-LATENCY", "WRITE-ACK", phy_settings.write_latency-1)
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fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
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fsm.delayed_enter("TRCD", "IDLE", timing_settings.tRCD-1)
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fsm.delayed_enter("PRE-REFRESH", "REFRESH", timing_settings.tRP-1)
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fsm.delayed_enter("POST-REFRESH", "IDLE", timing_settings.tRFC-1)
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# DFI commands
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for phase in dfi.phases:
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if hasattr(phase, "reset_n"):
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self.comb += phase.reset_n.eq(1)
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if hasattr(phase, "odt"):
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self.comb += phase.odt.eq(1)
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self.comb += [
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phase.cke.eq(1),
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phase.cs_n.eq(0),
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phase.bank.eq(slicer.bank(bus.adr)),
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If(precharge_all,
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phase.address.eq(2**10)
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).Elif(activate,
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phase.address.eq(slicer.row(bus.adr))
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).Elif(write | read,
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phase.address.eq(slicer.col(bus.adr))
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)
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]
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# DFI datapath
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self.comb += [
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bus.dat_r.eq(Cat(phase.rddata for phase in dfi.phases)),
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Cat(phase.wrdata for phase in dfi.phases).eq(bus.dat_w),
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Cat(phase.wrdata_mask for phase in dfi.phases).eq(~bus.sel),
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]
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