modules: add other RDIMM modules
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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@ -1078,9 +1078,11 @@ class HMA82GR7DJR4N(DDR4RegisteredModule):
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nrows = 131072
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 4.9), tZQCS=(128, 80))
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trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
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trfc = {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
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technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, 5), tRRD=(4, 4.9), tZQCS=(128, 80))
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speedgrade_timings = {
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"3200": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=416, tFAW=30, tRAS=32),
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"3200": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=trfc, tFAW=10, tRAS=32),
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}
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speedgrade_timings["default"] = speedgrade_timings["3200"]
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@ -1088,6 +1090,26 @@ class HMA84GR7DJR4N(HMA82GR7DJR4N): pass
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# This module is similar to HMA82GR7DJR4N, with the exception that it is a dual-rank module. The rank number
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# can be specified in the PHY settings.
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class M393A2K40DB3(DDR4RegisteredModule):
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# geometry
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ngroupbanks = 4
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ngroups = 4
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nbanks = ngroups * ngroupbanks
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nrows = 131072
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ncols = 1024
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# timings
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trefi = {"1x": 64e6/8192, "2x": (64e6/8192)/2, "4x": (64e6/8192)/4}
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trfc = {"1x": (None, 350), "2x": (None, 260), "4x": (None, 160)}
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technology_timings = _TechnologyTimings(tREFI=trefi, tWTR=(4, 7.5), tCCD=(4, 5), tRRD=(4, 4.9), tZQCS=(128, 80))
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speedgrade_timings = {
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"3200": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=15, tRFC=trfc, tFAW=10, tRAS=32),
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}
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speedgrade_timings["default"] = speedgrade_timings["3200"]
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class M393A4K40DB3(M393A2K40DB3): pass
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# This module is similar to M393A2K40DB3, with the exception that it is a dual-rank module. The rank number
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# can be specified in the PHY settings.
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# LPDDR4 -------------------------------------------------------------------------------------------
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class MT53E256M16D1(SDRAMModule):
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