test/test_fifo: add comments.
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@ -29,6 +29,7 @@ class TestFIFO(unittest.TestCase):
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# _LiteDRAMFIFOCtrl ----------------------------------------------------------------------------
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# _LiteDRAMFIFOCtrl ----------------------------------------------------------------------------
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def test_fifo_ctrl_address_changes(self):
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def test_fifo_ctrl_address_changes(self):
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# Verify FIFOCtrl address changes.
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# We are ignoring thresholds (so readable/writable signals)
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# We are ignoring thresholds (so readable/writable signals)
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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@ -64,6 +65,7 @@ class TestFIFO(unittest.TestCase):
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run_simulation(dut, generators)
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run_simulation(dut, generators)
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def test_fifo_ctrl_level_changes(self):
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def test_fifo_ctrl_level_changes(self):
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# Verify FIFOCtrl level changes.
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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dut = _LiteDRAMFIFOCtrl(base=0, depth=16, read_threshold=0, write_threshold=16)
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def main_generator():
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def main_generator():
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@ -140,12 +142,15 @@ class TestFIFO(unittest.TestCase):
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self.assertEqual(dut.memory.mem, mem_expected)
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self.assertEqual(dut.memory.mem, mem_expected)
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def test_fifo_writer_sequence(self):
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def test_fifo_writer_sequence(self):
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# Verify simple FIFOWriter sequence.
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self.fifo_writer_test(sequence_len=48, depth=64, write_threshold=64)
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self.fifo_writer_test(sequence_len=48, depth=64, write_threshold=64)
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def test_fifo_writer_address_wraps(self):
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def test_fifo_writer_address_wraps(self):
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# Verify FIFOWriter sequence with address wraps.
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self.fifo_writer_test(sequence_len=48, depth=32, write_threshold=64)
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self.fifo_writer_test(sequence_len=48, depth=32, write_threshold=64)
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def test_fifo_writer_stops_after_threshold(self):
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def test_fifo_writer_stops_after_threshold(self):
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# Verify FIFOWriter sequence with stop after threshold is reached.
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with self.assertRaises(TimeoutError):
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with self.assertRaises(TimeoutError):
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self.fifo_writer_test(sequence_len=48, depth=32, write_threshold=32)
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self.fifo_writer_test(sequence_len=48, depth=32, write_threshold=32)
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@ -205,12 +210,15 @@ class TestFIFO(unittest.TestCase):
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self.assertEqual(read_data, read_data_expected)
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self.assertEqual(read_data, read_data_expected)
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def test_fifo_reader_sequence(self):
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def test_fifo_reader_sequence(self):
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# Verify simple FIFOReader sequence.
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self.fifo_reader_test(sequence_len=48, depth=64, read_threshold=0)
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self.fifo_reader_test(sequence_len=48, depth=64, read_threshold=0)
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def test_fifo_reader_address_wraps(self):
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def test_fifo_reader_address_wraps(self):
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# Verify FIFOReader sequence with address wraps.
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=0)
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=0)
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def test_fifo_reader_requires_threshold(self):
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def test_fifo_reader_requires_threshold(self):
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# Verify FIFOReader sequence with start after threshold is reached.
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with self.assertRaises(TimeoutError):
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with self.assertRaises(TimeoutError):
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=8)
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self.fifo_reader_test(sequence_len=48, depth=32, read_threshold=8)
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# Will work after we perform the initial writes
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# Will work after we perform the initial writes
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@ -219,10 +227,11 @@ class TestFIFO(unittest.TestCase):
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# LiteDRAMFIFO ---------------------------------------------------------------------------------
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# LiteDRAMFIFO ---------------------------------------------------------------------------------
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def test_fifo_default_thresholds(self):
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def test_fifo_default_thresholds(self):
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# Verify FIFO with default threshold.
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# Defaults: read_threshold=0, write_threshold=depth
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# Defaults: read_threshold=0, write_threshold=depth
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read_threshold, write_threshold = (0, 128)
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read_threshold, write_threshold = (0, 128)
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write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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fifo = LiteDRAMFIFO(data_width=32, base=0, depth=write_threshold,
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fifo = LiteDRAMFIFO(data_width=32, base=0, depth=write_threshold,
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write_port = write_port,
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write_port = write_port,
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read_port = read_port)
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read_port = read_port)
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@ -242,10 +251,11 @@ class TestFIFO(unittest.TestCase):
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run_simulation(fifo, [generator(), checker])
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run_simulation(fifo, [generator(), checker])
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def test_fifo(self):
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def test_fifo(self):
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# Verify FIFO.
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class DUT(Module):
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class DUT(Module):
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def __init__(self):
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def __init__(self):
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.write_port = LiteDRAMNativeWritePort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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self.read_port = LiteDRAMNativeReadPort(address_width=32, data_width=32)
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self.submodules.fifo = LiteDRAMFIFO(
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self.submodules.fifo = LiteDRAMFIFO(
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data_width = 32,
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data_width = 32,
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depth = 32,
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depth = 32,
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