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frontend/bist: fix for data_width < 31 (16 bits SDRAMs)

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This commit is contained in:
Florent Kermarrec 2019-01-18 17:56:32 +01:00
parent b4c552a77f
commit 031746a53c
1 changed files with 2 additions and 1 deletions
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3
litedram/frontend/bist.py
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@ -337,12 +337,13 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
),
NextValue(self.ticks, 0)
)
data_fsm.act("RUN",
dma.source.ready.eq(1),
If(dma.source.valid,
data_gen.ce.eq(1),
NextValue(data_counter, data_counter + 1),
If(dma.source.data != data_gen.o,
If(dma.source.data != data_gen.o[:min(len(data_gen.o), dram_port.data_width)],
NextValue(self.errors, self.errors + 1)
),
If(data_counter == (self.length[ashift:] - 1),