Ensure out of order is on a per-bank basis
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@ -114,6 +114,8 @@ class LiteDRAMPort:
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self.lock = Signal()
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self.lock = Signal()
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self.reorder = reorder
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self.cmd = stream.Endpoint(cmd_description(aw))
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self.cmd = stream.Endpoint(cmd_description(aw))
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self.wdata = stream.Endpoint(wdata_description(dw, reorder))
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self.wdata = stream.Endpoint(wdata_description(dw, reorder))
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self.rdata = stream.Endpoint(rdata_description(dw, reorder))
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self.rdata = stream.Endpoint(rdata_description(dw, reorder))
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@ -78,14 +78,15 @@ class LiteDRAMCrossbar(Module):
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master_locked = []
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master_locked = []
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for nm, master in enumerate(self.masters):
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for nm, master in enumerate(self.masters):
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locked = 0
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locked = 0
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for other_nb, other_arbiter in enumerate(arbiters):
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if not master.reorder:
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if other_nb != nb:
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for other_nb, other_arbiter in enumerate(arbiters):
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other_bank = getattr(controller, "bank"+str(other_nb))
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if other_nb != nb:
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locked = locked | (other_bank.lock & (other_arbiter.grant == nm))
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other_bank = getattr(controller, "bank"+str(other_nb))
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locked = locked | (other_bank.lock & (other_arbiter.grant == nm))
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master_locked.append(locked)
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master_locked.append(locked)
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# arbitrate
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# arbitrate
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bank_selected = [(ba == nb) for ba, locked in zip(m_ba, master_locked)]
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bank_selected = [(ba == nb) & ~locked for ba, locked in zip(m_ba, master_locked)]
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bank_requested = [bs & master.cmd.valid for bs, master in zip(bank_selected, self.masters)]
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bank_requested = [bs & master.cmd.valid for bs, master in zip(bank_selected, self.masters)]
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self.comb += [
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self.comb += [
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arbiter.request.eq(Cat(*bank_requested)),
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arbiter.request.eq(Cat(*bank_requested)),
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