Ensure out of order is on a per-bank basis

This commit is contained in:
2018-08-10 16:35:16 -04:00
parent 86b3e2d2ef
commit 03a2ad6bdc
2 changed files with 8 additions and 5 deletions

View File

@ -114,6 +114,8 @@ class LiteDRAMPort:
self.lock = Signal()
self.reorder = reorder
self.cmd = stream.Endpoint(cmd_description(aw))
self.wdata = stream.Endpoint(wdata_description(dw, reorder))
self.rdata = stream.Endpoint(rdata_description(dw, reorder))

View File

@ -78,6 +78,7 @@ class LiteDRAMCrossbar(Module):
master_locked = []
for nm, master in enumerate(self.masters):
locked = 0
if not master.reorder:
for other_nb, other_arbiter in enumerate(arbiters):
if other_nb != nb:
other_bank = getattr(controller, "bank"+str(other_nb))
@ -85,7 +86,7 @@ class LiteDRAMCrossbar(Module):
master_locked.append(locked)
# arbitrate
bank_selected = [(ba == nb) for ba, locked in zip(m_ba, master_locked)]
bank_selected = [(ba == nb) & ~locked for ba, locked in zip(m_ba, master_locked)]
bank_requested = [bs & master.cmd.valid for bs, master in zip(bank_selected, self.masters)]
self.comb += [
arbiter.request.eq(Cat(*bank_requested)),