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Merge pull request #43 from enjoy-digital/EfficencyFixes 

Bank valid/ready refactor
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enjoy-digital 2018-09-23 09:40:14 +02:00 committed by GitHub
parent c12404e00c c4bd842cdf
commit 04aa04d123
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2 changed files with 23 additions and 27 deletions
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8
litedram/core/bankmachine.py
View File

@ -31,8 +31,6 @@ class BankMachine(Module):
self.req = req = Record(cmd_layout(aw)) self.req = req = Record(cmd_layout(aw))
self.refresh_req = Signal() self.refresh_req = Signal()
self.refresh_gnt = Signal() self.refresh_gnt = Signal()
self.ras_allowed = ras_allowed = Signal()
self.cas_allowed = cas_allowed = Signal()
a = settings.geom.addressbits a = settings.geom.addressbits
ba = settings.geom.bankbits + log2_int(nranks) ba = settings.geom.bankbits + log2_int(nranks)
self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba)) self.cmd = cmd = stream.Endpoint(cmd_request_rw_layout(a, ba))
@ -108,7 +106,6 @@ class BankMachine(Module):
).Elif(cmd_buffer.source.valid, ).Elif(cmd_buffer.source.valid,
If(has_openrow, If(has_openrow,
If(hit, If(hit,
If(cas_allowed,
cmd.valid.eq(1), cmd.valid.eq(1),
If(cmd_buffer.source.we, If(cmd_buffer.source.we,
req.wdata_ready.eq(cmd.ready), req.wdata_ready.eq(cmd.ready),
@ -122,7 +119,6 @@ class BankMachine(Module):
If(cmd.ready & auto_precharge, If(cmd.ready & auto_precharge,
NextState("AUTOPRECHARGE") NextState("AUTOPRECHARGE")
) )
)
).Else( ).Else(
NextState("PRECHARGE") NextState("PRECHARGE")
) )
@ -153,9 +149,9 @@ class BankMachine(Module):
fsm.act("ACTIVATE", fsm.act("ACTIVATE",
sel_row_addr.eq(1), sel_row_addr.eq(1),
track_open.eq(1), track_open.eq(1),
cmd.valid.eq(ras_allowed), cmd.valid.eq(1),
cmd.is_cmd.eq(1), cmd.is_cmd.eq(1),
If(cmd.ready & ras_allowed, If(cmd.ready,
NextState("TRCD") NextState("TRCD")
), ),
cmd.ras.eq(1) cmd.ras.eq(1)

18
litedram/core/multiplexer.py
View File

@ -63,7 +63,9 @@ class _CommandChooser(Module):
If(cmd.valid & cmd.ready & (arbiter.grant == i), If(cmd.valid & cmd.ready & (arbiter.grant == i),
request.ready.eq(1) request.ready.eq(1)
) )
self.comb += arbiter.ce.eq(cmd.ready) # Arbitrate if we're accepting commands, *or* if we are not but the current selection is not valid
# This is to ensure that a valid command is selected when cmd.ready goes high
self.comb += arbiter.ce.eq(cmd.ready | ~cmd.valid)
# helpers # helpers
def accept(self): def accept(self):
@ -91,7 +93,7 @@ class _Steerer(Module):
if not hasattr(cmd, "valid"): if not hasattr(cmd, "valid"):
return 0 return 0
else: else:
return cmd.valid & getattr(cmd, attr) return cmd.valid & cmd.ready & getattr(cmd, attr)
for phase, sel in zip(dfi.phases, self.sel): for phase, sel in zip(dfi.phases, self.sel):
nranks = len(phase.cs_n) nranks = len(phase.cs_n)
@ -114,9 +116,9 @@ class _Steerer(Module):
self.sync += [ self.sync += [
phase.address.eq(Array(cmd.a for cmd in commands)[sel]), phase.address.eq(Array(cmd.a for cmd in commands)[sel]),
phase.cas_n.eq(~Array(cmd.cas for cmd in commands)[sel]), phase.cas_n.eq(~Array(valid_and(cmd, "cas") for cmd in commands)[sel]),
phase.ras_n.eq(~Array(cmd.ras for cmd in commands)[sel]), phase.ras_n.eq(~Array(valid_and(cmd, "ras") for cmd in commands)[sel]),
phase.we_n.eq(~Array(cmd.we for cmd in commands)[sel]) phase.we_n.eq(~Array(valid_and(cmd, "we") for cmd in commands)[sel])
] ]
rddata_ens = Array(valid_and(cmd, "is_read") for cmd in commands) rddata_ens = Array(valid_and(cmd, "is_read") for cmd in commands)
@ -218,7 +220,6 @@ class Multiplexer(Module, AutoCSR):
# RAS control # RAS control
self.comb += ras_allowed.eq(trrdcon.ready & tfawcon.ready) self.comb += ras_allowed.eq(trrdcon.ready & tfawcon.ready)
self.comb += [bm.ras_allowed.eq(ras_allowed) for bm in bank_machines]
# tCCD timing (Column to Column delay) # tCCD timing (Column to Column delay)
self.submodules.tccdcon = tccdcon = tXXDController(settings.timing.tCCD) self.submodules.tccdcon = tccdcon = tXXDController(settings.timing.tCCD)
@ -226,7 +227,6 @@ class Multiplexer(Module, AutoCSR):
# CAS control # CAS control
self.comb += cas_allowed.eq(tccdcon.ready) self.comb += cas_allowed.eq(tccdcon.ready)
self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
# tWTR timing (Write to Read delay) # tWTR timing (Write to Read delay)
self.submodules.twtrcon = twtrcon = tXXDController( self.submodules.twtrcon = twtrcon = tXXDController(
@ -306,7 +306,7 @@ class Multiplexer(Module, AutoCSR):
choose_req.want_reads.eq(1), choose_req.want_reads.eq(1),
choose_cmd.want_activates.eq(ras_allowed), choose_cmd.want_activates.eq(ras_allowed),
choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed), choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed),
choose_req.cmd.ready.eq(1), choose_req.cmd.ready.eq(cas_allowed),
steerer_sel(steerer, "read"), steerer_sel(steerer, "read"),
If(write_available, If(write_available,
# TODO: switch only after several cycles of ~read_available? # TODO: switch only after several cycles of ~read_available?
@ -323,7 +323,7 @@ class Multiplexer(Module, AutoCSR):
choose_req.want_writes.eq(1), choose_req.want_writes.eq(1),
choose_cmd.want_activates.eq(ras_allowed), choose_cmd.want_activates.eq(ras_allowed),
choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed), choose_cmd.cmd.ready.eq(~choose_cmd.activate() | ras_allowed),
choose_req.cmd.ready.eq(1), choose_req.cmd.ready.eq(cas_allowed),
steerer_sel(steerer, "write"), steerer_sel(steerer, "write"),
If(read_available, If(read_available,
If(~write_available | max_write_time, If(~write_available | max_write_time,