lpddr4: improve documentation
This commit is contained in:
Jędrzej Boczar
parent
1b65e858b3
commit
052dc19246
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@ -14,6 +14,7 @@ from litedram.phy.lpddr4.commands import DFIPhaseAdapter
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class Latency:
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"""Used to specify latency for LPDDR4PHY"""
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def __init__(self, sys, sys8x=0):
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self.sys = sys + sys8x//8
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self.sys8x = sys8x % 8
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@ -47,6 +48,42 @@ class LPDDR4Output:
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class LPDDR4PHY(Module, AutoCSR):
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"""Core of LPDDR4 PHYs.
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This class implements all the logic required to convert DFI to/from pads.
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It works in a single clock domain. Signals for DRAM pads are stored in
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LPDDR4Output (self.out). Concrete implementations of LPDDR4 PHYs derive
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from this class and perform (de-)serialization of LPDDR4Output to pads.
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DFI commands
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------------
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Not all LPDDR4 commands map directly to DFI commands. For this reason ZQC
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is treated specially in that DFI ZQC is translated into LPDDR4 MPC and has
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different interpretation depending on DFI.address.
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Also, due to the fact that LPDDR4 has 256-bit Mode Register space, the DFI
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MRS command encodes both register address *and* value in DFI.address (instead
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of the default in LiteDRAM to split them between DFI.address and DFI.bank).
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Refer to the documentation in `commands.py` for further information.
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Parameters
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----------
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pads : object
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Object containing LPDDR4 pads.
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sys_clk_freq : float
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Frequency of memory controller's clock.
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ser_latency : Latency
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Additional latency introduced due to signal serialization.
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des_latency : Latency
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Additional latency introduced during signal deserialization.
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phytype : str
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Name of the PHY (concrete implementation).
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masked_write : bool
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Use MASKED-WRITE commands if True else use WRITE commands (data masking will not work).
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cmd_delay : int
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Used to force cmd delay during initialization in BIOS.
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"""
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def __init__(self, pads, *,
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sys_clk_freq, ser_latency, des_latency, phytype,
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masked_write=True, cmd_delay=None):
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@ -32,8 +32,25 @@ class DFIPhaseAdapter(Module):
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consist only of a single "small command". To make counting DRAM timings easier, such
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a "small command" shall be sent on the 2nd slot (i.e. 3rd and 4th cycle). All timings
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are then counted starting from CS low on the 4th cycle.
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"""
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Parameters
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----------
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dfi_phase : Record(dfi.phase_description), in
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Input from a single DFI phase.
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masked_write : bool
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Specifies how DFI write command (cas_n=0, ras_n=1, we_n=0) is interpreted, either
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as LPDDR4 WRITE or MASKED-WRITE. MASKED-WRITE requires larger tCCD, but WRITE does
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not permit masking of data, so if masking is needed MASKED-WRITE has to be used.
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Attributes
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----------
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cs : Signal(4), out
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Values of CS on 4 subsequent DRAM SDR clock cycles.
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ca : Array(4, Signal(6)), out
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Values of CA[5:0] on 4 subsequent DRAM SDR clock cycles.
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valid : Signal, out
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Indicates that a valid command is presented on the `cs` and `ca` outputs.
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"""
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def __init__(self, dfi_phase, masked_write=True):
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# CS/CA values for 4 SDR cycles
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self.cs = Signal(4)
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@ -90,11 +107,20 @@ class Command(Module):
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Decodes a command from single DFI phase into LPDDR4 "small command"
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consisting of 2 CS values and 2 CA[5:0] values.
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LPDDR4 "small commands" are transmited over 2 clock cycles. In first
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LPDDR4 "small commands" are transmited over 2 clock cycles. In the first
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cycle CS is driven high and in the second cycle it stays low. In each
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of the cycles the bits on CA[5:0] are latched and interpreted differently.
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This module translates a DFI command into the values of CS/CA that shall
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be transmitted over 2 DRAM clock cycles.
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Attributes
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----------
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dfi : Record(dfi.phase_description), in
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Input from single DFI phase.
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cs : Signal(2), out
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CS values over 2 subsequent DRAM SDR clock cycles.
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ca : Array(2, Signal(6)), out
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CA[5:0] values over 2 subsequent DRAM SDR clock cycles.
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"""
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# String description of 1st and 2nd edge of each command, later parsed to
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@ -126,9 +152,9 @@ class Command(Module):
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def set(self, cmd):
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ops = []
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for i, description in enumerate(self.TRUTH_TABLE[cmd]):
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for j, bit in enumerate(description.split()):
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ops.append(self.ca[i][j].eq(self.parse_bit(bit, is_mpc=cmd == "MPC")))
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for cyc, description in enumerate(self.TRUTH_TABLE[cmd]):
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for bit, bit_desc in enumerate(description.split()):
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ops.append(self.ca[cyc][bit].eq(self.parse_bit(bit_desc)))
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if cmd != "DESELECT":
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ops.append(self.cs[0].eq(1))
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return ops
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@ -14,18 +14,58 @@ from litedram.phy.lpddr4.commands import MPC
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def log_level_getter(log_level):
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"""Parse logging level description
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Log level can be presented in a simple form (e.g. `--log-level=DEBUG`) to specify
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the same level for all modules, or can set different levels for different modules
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e.g. `--log-level=all=INFO,data=DEBUG`.
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"""
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def get_level(name):
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return getattr(SimLogger, name.upper())
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# simple log_level, e.g. "INFO"
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if "=" not in log_level:
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if "=" not in log_level: # simple log_level, e.g. "INFO"
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return lambda _: get_level(log_level)
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# parse log_level in the per-module form, e.g. "--log-level=all=INFO,data=DEBUG"
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per_module = dict(part.split("=") for part in log_level.strip().split(","))
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return lambda module: get_level(per_module.get(module, per_module.get("all", None)))
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class LPDDR4Sim(Module, AutoCSR):
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def __init__(self, pads, *, sys_clk_freq, disable_delay, settings, log_level):
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"""LPDDR4 DRAM simulator
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This module simulates an LPDDR4 DRAM chip to aid LPDDR4 PHY development/testing.
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It does not aim to simulate the internals of an LPDDR4 chip, rather it's behavior
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as seen by the PHY.
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The simulator monitors CS/CA pads listening for LPDDR4 commands and updates the module
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state depending on the command received. Any unexpected sequences are logged in simulation
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as errors/warnings. On read/write commands the data simulation module is triggered
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after CL/CWL and a data burst is handled, updating memory state.
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The simulator requires the following clock domains:
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sys8x: 8x the memory controller clock frequency, phase aligned.
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sys8x_90: Phase shifted by 90 degrees vs sys8x.
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sys8x_ddr: Phase aligned with sys8x, double the frequency.
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sys8x_90_ddr: Phase aligned with sys8x_90, double the frequency.
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Parameters
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----------
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pads : LPDDR4SimulationPads
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DRAM pads
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sys_clk_freq : float
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System clock frequency
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cl : int
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LPDDR4 read latency (RL).
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cwl : int
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LPDDR4 write latency (WL).
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disable_delay : bool
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Disable checking of timings that rely on long CPU delays (mostly init sequence
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timings). This is useful when running LiteX BIOS with CONFIG_DISABLE_DELAYS on.
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log_level : str
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SimLogger initial logging level (formatted for parsing with `log_level_getter`).
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"""
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def __init__(self, pads, *, sys_clk_freq, cl, cwl, disable_delay, log_level):
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log_level = log_level_getter(log_level)
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cd_cmd = "sys8x_90"
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@ -34,12 +74,12 @@ class LPDDR4Sim(Module, AutoCSR):
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cd_dq_rd = "sys8x_90_ddr"
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cd_dqs_rd = "sys8x_ddr"
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self.submodules.data = ClockDomainCrossing(
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self.submodules.data_cdc = ClockDomainCrossing(
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[("we", 1), ("masked", 1), ("bank", 3), ("row", 17), ("col", 10)],
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cd_from=cd_cmd, cd_to=cd_dq_wr)
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cmd = CommandsSim(pads,
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data_cdc = self.data,
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data_cdc = self.data_cdc,
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clk_freq = 8*sys_clk_freq,
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log_level = log_level("cmd"),
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init_delays = not disable_delay,
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@ -52,8 +92,8 @@ class LPDDR4Sim(Module, AutoCSR):
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cd_dq_rd = cd_dq_rd,
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cd_dqs_rd = cd_dqs_rd,
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clk_freq = 2*8*sys_clk_freq,
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cl = settings.phy.cl,
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cwl = settings.phy.cwl,
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cl = cl,
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cwl = cwl,
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log_level = log_level("data"),
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)
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self.submodules.data = ClockDomainsRenamer(cd_dq_wr)(data)
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@ -61,10 +101,14 @@ class LPDDR4Sim(Module, AutoCSR):
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# Commands -----------------------------------------------------------------------------------------
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class PulseTiming(Module):
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# Works like tXXDController with the following differences:
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# * countdown triggered by a low to high pulse on `trigger`
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# * `ready` is initially low, only after a trigger it can become high
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# * provides `ready_p` which is high only for 1 cycle when `ready` becomes high
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"""Timing monitor with pulse input/output
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This module works like `tXXDController` with the following differences:
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* countdown triggered by a low to high pulse on `trigger`
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* `ready` is initially low, only after a trigger it can become high
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* provides `ready_p` which is high only for 1 cycle when `ready` becomes high
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"""
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def __init__(self, t):
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self.trigger = Signal()
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self.ready = Signal()
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@ -83,7 +127,16 @@ class PulseTiming(Module):
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]
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class CommandsSim(Module, AutoCSR): # clock domain: clk_p
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class CommandsSim(Module, AutoCSR):
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"""Command simulation
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This module interprets LPDDR4 commands found on the CS/CA pads. It keeps track of currently
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opened rows (per bank) and stores the values of Mode Registers. It also checks that the DRAM
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initialization sequence is performed according to specification. On any read/write commands
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signals indicating a burst are sent to the data simulator for handling.
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Command simulator should work in the clock domain of `pads.clk_p` (SDR).
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"""
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def __init__(self, pads, data_cdc, *, clk_freq, log_level, init_delays=False):
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self.submodules.log = log = SimLogger(log_level=log_level, clk_freq=clk_freq)
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self.log.add_csrs()
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@ -439,7 +492,15 @@ class CommandsSim(Module, AutoCSR): # clock domain: clk_p
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# Data ---------------------------------------------------------------------------------------------
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class DataSim(Module, AutoCSR): # clock domain: ddr
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class DataSim(Module, AutoCSR):
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"""Data simulator
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This module is responsible for handling read/write bursts. It's operation has to be triggered
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by the command simulator. Data is stored in an internal memory, no state is verified (row
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open/closed, etc.), this must be checked by command simulation.
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This module runs with DDR clocks (simulation clocks with double the frequency of `pads.clk_p`).
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"""
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def __init__(self, pads, cmds_sim, *, cd_dq_wr, cd_dq_rd, cd_dqs_wr, cd_dqs_rd, cl, cwl, clk_freq, log_level):
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self.submodules.log = log = SimLogger(log_level=log_level, clk_freq=clk_freq)
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self.log.add_csrs()
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@ -5,6 +5,13 @@ from litedram.phy.lpddr4.basephy import LPDDR4PHY, DoubleRateLPDDR4PHY, Latency
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class LPDDR4SimulationPads(Module):
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"""Pads for simulation purpose
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To avoid simulate tristate behavior of DQ/DQS/DMI pins separate input and output
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pins (_i/_o) are provided. Output pins are to be driven by the PHY and input pins
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are to be driven by the DRAM simulator. This module sets the actual values on pins
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`dq`, `dqs` and `dmi` based on output enable signals.
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"""
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def __init__(self, databits=16):
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self.clk_p = Signal()
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self.clk_n = Signal()
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@ -36,6 +43,17 @@ class LPDDR4SimulationPads(Module):
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class _LPDDR4SimPHYMixin:
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"""Common serialization logic for simulation PHYs
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This mixin provides `do_serialization` method for constructing the boilerplate
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serialization/deserialization paths for a simulation PHY. This can serve as a
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reference for implemeing PHYs for concrete FPGAs.
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To make the (de-)serialization work in simulation two additional clock domains
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are required: `sys8x_ddr` and `sys8x_90_ddr`. These correspond to `sys8x` and
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`sys8x_90`, are phase aligned with them and at twice their frequency. These
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clock domains are requried to implement DDR (de-)serialization at 8x sys clock.
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"""
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def _add_name(self, prefix, kwargs):
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name = prefix + "_" + kwargs.pop("name", "")
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kwargs["name"] = name.strip("_")
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@ -102,6 +120,7 @@ class _LPDDR4SimPHYMixin:
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class LPDDR4SimPHY(_LPDDR4SimPHYMixin, LPDDR4PHY):
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"""LPDDR4 simulation PHY with direct 16:1 serializers"""
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def __init__(self, aligned_reset_zero=False, **kwargs):
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pads = LPDDR4SimulationPads()
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self.submodules += pads
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@ -119,6 +138,11 @@ class LPDDR4SimPHY(_LPDDR4SimPHYMixin, LPDDR4PHY):
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class DoubleRateLPDDR4SimPHY(_LPDDR4SimPHYMixin, DoubleRateLPDDR4PHY):
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"""LPDDR4 simulation PHY basing of DoubleRateLPDDR4PHY
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`DoubleRateLPDDR4PHY` performs a single serialization step between `sys` and `sys2x`,
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so this PHY wrapper has to do the serialization between `sys2x` and `sys8x` (SDR/DDR).
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"""
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def __init__(self, aligned_reset_zero=False, **kwargs):
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pads = LPDDR4SimulationPads()
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self.submodules += pads
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@ -103,9 +103,13 @@ def get_clocks(sys_clk_freq):
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# SoC ----------------------------------------------------------------------------------------------
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class SimSoC(SoCCore):
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def __init__(self, clocks, log_level, auto_precharge=False, with_refresh=True, trace_reset=0,
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disable_delay=False, masked_write=True, double_rate_phy=False, finish_after_memtest=False,
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**kwargs):
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"""Simulation of SoC with LPDDR4 DRAM
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This is a SoC used to run Verilator-based simulations of LiteDRAM with a simulated LPDDR4 chip.
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"""
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def __init__(self, clocks, log_level,
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auto_precharge=False, with_refresh=True, trace_reset=0, disable_delay=False,
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masked_write=True, double_rate_phy=False, finish_after_memtest=False, **kwargs):
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platform = Platform()
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sys_clk_freq = clocks["sys"]["freq_hz"]
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@ -161,7 +165,8 @@ class SimSoC(SoCCore):
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# LPDDR4 Sim -------------------------------------------------------------------------------
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self.submodules.lpddr4sim = LPDDR4Sim(
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pads = self.ddrphy.pads,
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settings = self.sdram.controller.settings,
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cl = self.sdram.controller.settings.phy.cl,
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cwl = self.sdram.controller.settings.phy.cwl,
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sys_clk_freq = sys_clk_freq,
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log_level = log_level,
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disable_delay = disable_delay,
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@ -172,6 +172,14 @@ class Deserializer(Module):
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class SimLogger(Module, AutoCSR):
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"""Logger for use in simulation
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This module allows for easier message logging when running simulation designs.
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The logger can be used from `comb` context so it the methods can be directly
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used inside `FSM` code. It also provides logging levels that can be used to
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filter messages, either by specifying the default `log_level` or in runtime
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by driving to the `level` signal or using a corresponding CSR.
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"""
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# Allows to use Display inside FSM and to filter log messages by level (statically or dynamically)
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DEBUG = 0
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INFO = 1
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