bench: uniformize targets with 125MHz clock and Etherbone.
This commit is contained in:
Florent Kermarrec
parent
0279b770ee
commit
06544c6547
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@ -22,6 +22,8 @@ from litex.soc.integration.builder import *
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoCSR):
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@ -59,7 +61,7 @@ class _CRG(Module, AutoCSR):
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(150e6)):
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def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
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platform = arty.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -67,7 +69,7 @@ class BenchSoC(SoCCore):
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integrated_rom_size = 0x8000,
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integrated_rom_mode = "rw",
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csr_data_width = 32,
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uart_name = "crossover")
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uart_name = uart)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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@ -86,7 +88,16 @@ class BenchSoC(SoCCore):
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)
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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if uart != "serial":
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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with_hw_init_reset = False)
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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@ -99,12 +110,15 @@ class BenchSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Bench on Arty A7")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--test", action="store_true", help="Run Test")
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parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
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parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
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parser.add_argument("--test", action="store_true", help="Run Full Bench")
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args = parser.parse_args()
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soc = BenchSoC()
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soc = BenchSoC(uart=args.uart)
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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@ -112,6 +126,14 @@ def main():
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.load_bios:
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from common import s7_load_bios
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s7_load_bios("build/arty/software/bios/bios.bin")
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if args.set_sys_clk is not None:
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from common import s7_set_sys_clk
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s7_set_sys_clk(clk_freq=float(args.config), vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if args.test:
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from common import s7_bench_test
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s7_bench_test(
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@ -59,7 +59,7 @@ class _CRG(Module, AutoCSR):
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, uart="crossover", sys_clk_freq=int(175e6)):
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def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
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platform = genesys2.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -22,6 +22,8 @@ from litex.soc.integration.builder import *
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from litedram.phy import s7ddrphy
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from litedram.modules import MT8JTF12864
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from liteeth.phy import LiteEthPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoCSR):
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@ -57,7 +59,7 @@ class _CRG(Module, AutoCSR):
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(175e6)):
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def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
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platform = kc705.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -86,6 +88,14 @@ class BenchSoC(SoCCore):
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHY(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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clk_freq = self.clk_freq)
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.submodules.leds = LedChaser(
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@ -97,9 +107,12 @@ class BenchSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Bench on KC705")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--test", action="store_true", help="Run Test")
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parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
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parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
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parser.add_argument("--test", action="store_true", help="Run Full Bench")
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args = parser.parse_args()
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soc = BenchSoC()
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@ -110,6 +123,14 @@ def main():
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.load_bios:
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from common import s7_load_bios
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s7_load_bios("build/kc705/software/bios/bios.bin")
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if args.set_sys_clk is not None:
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from common import us_set_sys_clk
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us_set_sys_clk(clk_freq=float(args.config), vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if args.test:
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from common import s7_bench_test
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s7_bench_test(
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@ -22,6 +22,8 @@ from litex.soc.cores.led import LedChaser
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from litedram.modules import EDY4016A
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from litedram.phy import usddrphy
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from liteeth.phy.ku_1000basex import KU_1000BASEX
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoCSR):
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@ -32,6 +34,7 @@ class _CRG(Module, AutoCSR):
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_uart = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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@ -41,6 +44,7 @@ class _CRG(Module, AutoCSR):
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main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
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main_pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
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main_pll.create_clkout(self.cd_uart, 100e6)
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main_pll.create_clkout(self.cd_eth, 200e6)
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main_pll.expose_drp()
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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@ -67,7 +71,7 @@ class _CRG(Module, AutoCSR):
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(175e6)):
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def __init__(self, uart="crossover", sys_clk_freq=int(125e6)):
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platform = kcu105.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -75,7 +79,7 @@ class BenchSoC(SoCCore):
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integrated_rom_size = 0x8000,
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integrated_rom_mode = "rw",
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csr_data_width = 32,
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uart_name = "crossover")
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uart_name = uart)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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@ -95,7 +99,17 @@ class BenchSoC(SoCCore):
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)
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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if uart != "serial":
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
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data_pads = self.platform.request("sfp", 0),
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sys_clk_freq = self.clk_freq)
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self.add_csr("ethphy")
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self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
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self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
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self.add_etherbone(phy=self.ethphy)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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@ -107,12 +121,15 @@ class BenchSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Bench on KCU105")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--test", action="store_true", help="Run Test")
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parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
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parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
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parser.add_argument("--test", action="store_true", help="Run Full Bench")
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args = parser.parse_args()
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soc = BenchSoC()
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soc = BenchSoC(uart=args.uart)
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builder = Builder(soc, csr_csv="csr.csv")
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builder.build(run=args.build)
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@ -120,6 +137,14 @@ def main():
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.load_bios:
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from common import s7_load_bios
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s7_load_bios("build/kcu105/software/bios/bios.bin")
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if args.set_sys_clk is not None:
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from common import us_set_sys_clk
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us_set_sys_clk(clk_freq=float(args.config), vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if args.test:
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from common import us_bench_test
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us_bench_test(
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