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frontend/crossbar: remove support of multiple controller (too complex and never used)

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This commit is contained in:
Florent Kermarrec 2016-04-29 17:06:43 +02:00
parent 47f2859091
commit 077043e310
1 changed files with 95 additions and 127 deletions
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68
litedram/frontend/crossbar.py
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@ -6,36 +6,27 @@ from litex.gen.genlib import roundrobin
from litedram.bus import *
def _getattr_all(l, attr):
it = iter(l)
r = getattr(next(it), attr)
for e in it:
if getattr(e, attr) != r:
raise ValueError
return r
class LiteDRAMCrossbar(Module):
def __init__(self, controllers, cba_shift):
self._controllers = controllers
def __init__(self, controller, cba_shift):
self._controller = controller
self._cba_shift = cba_shift
self._rca_bits = _getattr_all(controllers, "aw")
self._dw = _getattr_all(controllers, "dw")
self._nbanks = _getattr_all(controllers, "nbanks")
self._req_queue_size = _getattr_all(controllers, "req_queue_size")
self._read_latency = _getattr_all(controllers, "read_latency")
self._write_latency = _getattr_all(controllers, "write_latency")
self._rca_bits = controller.aw
self._dw = controller.dw
self._nbanks = controller.nbanks
self._req_queue_size = controller.req_queue_size
self._read_latency = controller.read_latency
self._write_latency = controller.write_latency
self._bank_bits = log2_int(self._nbanks, False)
self._controller_bits = log2_int(len(self._controllers), False)
self._masters = []
def get_master(self):
if self.finalized:
raise FinalizeError
lasmi_master = Interface(self._rca_bits + self._bank_bits + self._controller_bits,
lasmi_master = Interface(self._rca_bits + self._bank_bits,
self._dw, 1, self._req_queue_size, self._read_latency, self._write_latency)
self._masters.append(lasmi_master)
return lasmi_master
@ -43,13 +34,11 @@ class LiteDRAMCrossbar(Module):
def do_finalize(self):
nmasters = len(self._masters)
m_ca, m_ba, m_rca = self._split_master_addresses(self._controller_bits,
self._bank_bits, self._rca_bits, self._cba_shift)
m_ba, m_rca = self._split_master_addresses(self._bank_bits,
self._rca_bits,
self._cba_shift)
for nc, controller in enumerate(self._controllers):
if self._controller_bits:
controller_selected = [ca == nc for ca in m_ca]
else:
controller = self._controller
controller_selected = [1]*nmasters
master_req_acks = [0]*nmasters
master_dat_w_acks = [0]*nmasters
@ -132,29 +121,15 @@ class LiteDRAMCrossbar(Module):
]
# route data reads
if self._controller_bits:
for master in self._masters:
controller_sel = Signal(self._controller_bits)
for nc, controller in enumerate(self._controllers):
for nb in range(nbanks):
bank = getattr(controller, "bank"+str(nb))
self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
for i in range(self._read_latency):
n_controller_sel = Signal(self._controller_bits)
self.sync += n_controller_sel.eq(controller_sel)
controller_sel = n_controller_sel
self.comb += master.dat_r.eq(Array(self._controllers)[controller_sel].dat_r)
else:
self.comb += [master.dat_r.eq(self._controllers[0].dat_r) for master in self._masters]
self.comb += [master.dat_r.eq(self._controller.dat_r) for master in self._masters]
def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
m_ca = [] # controller address
def _split_master_addresses(self, bank_bits, rca_bits, cba_shift):
m_ba = [] # bank address
m_rca = [] # row and column address
for master in self._masters:
cba = Signal(self._controller_bits + self._bank_bits)
cba = Signal(self._bank_bits)
rca = Signal(self._rca_bits)
cba_upper = cba_shift + controller_bits + bank_bits
cba_upper = cba_shift + bank_bits
self.comb += cba.eq(master.adr[cba_shift:cba_upper])
if cba_shift < self._rca_bits:
if cba_shift:
@ -164,15 +139,8 @@ class LiteDRAMCrossbar(Module):
else:
self.comb += rca.eq(master.adr[:cba_shift])
if self._controller_bits:
ca = Signal(self._controller_bits)
ba = Signal(self._bank_bits)
self.comb += Cat(ba, ca).eq(cba)
else:
ca = None
ba = cba
m_ca.append(ca)
m_ba.append(ba)
m_rca.append(rca)
return m_ca, m_ba, m_rca
return m_ba, m_rca