phy/ecp5ddrphy: simplify/cleanup.
This commit is contained in:
Florent Kermarrec
parent
62915cd777
commit
12a017ff9c
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@ -139,7 +139,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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# # #
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bl8_sel = Signal()
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bl8_chunk = Signal()
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rddata_en = Signal(self.settings.read_latency)
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wrdata_en = Signal(cwl_sys_latency + 4)
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@ -203,10 +203,10 @@ class ECP5DDRPHY(Module, AutoCSR):
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)
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# DQ ---------------------------------------------------------------------------------------
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oe_dq = Signal()
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oe_dqs = Signal()
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dqs_postamble = Signal()
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dqs_preamble = Signal()
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dq_oe = Signal()
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dqs_oe = Signal()
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dqs_pattern = DQSPattern()
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self.submodules += dqs_pattern
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for i in range(databits//8):
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# DQSBUFM
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dqs_i = Signal()
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@ -286,15 +286,11 @@ class ECP5DDRPHY(Module, AutoCSR):
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burstdet_d = Signal()
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self.sync += [
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burstdet_d.eq(burstdet),
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If(self._burstdet_clr.re,
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self._burstdet_seen.status[i].eq(0)
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).Elif(burstdet & ~burstdet_d,
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self._burstdet_seen.status[i].eq(1)
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)
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If(self._burstdet_clr.re, self._burstdet_seen.status[i].eq(0)),
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If(burstdet & ~burstdet_d, self._burstdet_seen.status[i].eq(1)),
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]
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# DQS and DM ---------------------------------------------------------------------------
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dqs_serdes_pattern = Signal(8, reset=0b1010)
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dm_o_data = Signal(8)
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dm_o_data_d = Signal(8)
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dm_o_data_muxed = Signal(4)
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@ -310,12 +306,10 @@ class ECP5DDRPHY(Module, AutoCSR):
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dfi.phases[1].wrdata_mask[3*databits//8+i]),
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)
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self.sync += dm_o_data_d.eq(dm_o_data)
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self.sync += \
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If(bl8_sel,
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dm_o_data_muxed.eq(dm_o_data_d[4:])
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).Else(
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dm_o_data_muxed.eq(dm_o_data[:4])
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)
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dm_bl8_cases = {}
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dm_bl8_cases[0] = dm_o_data_muxed.eq(dm_o_data[:4])
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dm_bl8_cases[1] = dm_o_data_muxed.eq(dm_o_data_d[4:])
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self.sync += Case(bl8_chunk, dm_bl8_cases)
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self.specials += Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys2x"),
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i_ECLK = ClockSignal("sys2x"),
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@ -336,10 +330,10 @@ class ECP5DDRPHY(Module, AutoCSR):
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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i_D0 = dqs_serdes_pattern[0],
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i_D1 = dqs_serdes_pattern[1],
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i_D2 = dqs_serdes_pattern[2],
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i_D3 = dqs_serdes_pattern[3],
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i_D0 = dqs_pattern.o[3],
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i_D1 = dqs_pattern.o[2],
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i_D2 = dqs_pattern.o[1],
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i_D3 = dqs_pattern.o[0],
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o_Q = dqs
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),
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Instance("TSHX2DQSA",
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@ -347,8 +341,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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i_T0 = ~(oe_dqs|dqs_postamble),
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i_T1 = ~(oe_dqs|dqs_preamble),
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i_T0 = ~dqs_oe,
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i_T1 = ~dqs_oe,
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o_Q = dqs_oe_n
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),
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Tristate(pads.dqs_p[i], dqs, ~dqs_oe_n, dqs_i)
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@ -375,12 +369,10 @@ class ECP5DDRPHY(Module, AutoCSR):
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dfi.phases[1].wrdata[3*databits+j])
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)
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self.sync += dq_o_data_d.eq(dq_o_data)
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self.sync += \
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If(bl8_sel,
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dq_o_data_muxed.eq(dq_o_data_d[4:])
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).Else(
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dq_o_data_muxed.eq(dq_o_data[:4])
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)
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dq_bl8_cases = {}
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dq_bl8_cases[0] = dq_o_data_muxed.eq(dq_o_data[:4])
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dq_bl8_cases[1] = dq_o_data_muxed.eq(dq_o_data_d[4:])
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self.sync += Case(bl8_chunk, dq_bl8_cases)
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_dq_i_data = Signal(4)
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self.specials += [
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Instance("ODDRX2DQA",
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@ -440,8 +432,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_T0 = ~oe_dq,
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i_T1 = ~oe_dq,
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i_T0 = ~dq_oe,
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i_T1 = ~dq_oe,
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o_Q = dq_oe_n,
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),
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Tristate(pads.dq[j], dq_o, ~dq_oe_n, dq_i)
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@ -472,12 +464,12 @@ class ECP5DDRPHY(Module, AutoCSR):
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wrdata_en_last = Signal.like(wrdata_en)
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self.comb += wrdata_en.eq(Cat(dfi.phases[self.settings.wrphase].wrdata_en, wrdata_en_last))
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self.sync += wrdata_en_last.eq(wrdata_en)
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self.sync += oe_dq.eq(wrdata_en[cwl_sys_latency:cwl_sys_latency + 4] != 0b0000)
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self.sync += bl8_sel.eq(wrdata_en[cwl_sys_latency])
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self.comb += oe_dqs.eq(oe_dq)
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self.sync += dq_oe.eq(wrdata_en[cwl_sys_latency:cwl_sys_latency + 4] != 0b0000)
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self.sync += bl8_chunk.eq(wrdata_en[cwl_sys_latency])
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self.comb += dqs_oe.eq(dq_oe)
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# Write DQS Postamble/Preamble Control Path ------------------------------------------------
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# Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
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# write.
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self.sync += dqs_preamble.eq( wrdata_en[cwl_sys_latency:-1] == 0b10)
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self.sync += dqs_postamble.eq(wrdata_en[cwl_sys_latency+1:] == 0b01)
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#self.sync += dqs_pattern.preamble.eq( wrdata_en[cwl_sys_latency:-1] == 0b10)
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#self.sync += dqs_pattern.postamble.eq(wrdata_en[cwl_sys_latency+1:] == 0b01)
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