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frontend/axi: addressing in bytes not internal dwords

This commit is contained in:
Florent Kermarrec 2018-08-27 11:05:37 +02:00
parent 06f841dc2a
commit 137061734b
1 changed files with 4 additions and 2 deletions
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6
litedram/frontend/axi.py
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@ -56,6 +56,8 @@ class LiteDRAMAXI2Native(Module):
# # # # # #
ashift = log2_int(port.data_width//8)
can_write = Signal() can_write = Signal()
can_read = Signal() can_read = Signal()
@ -121,12 +123,12 @@ class LiteDRAMAXI2Native(Module):
port.cmd.valid.eq(axi.ar.valid & can_read), port.cmd.valid.eq(axi.ar.valid & can_read),
axi.ar.ready.eq(port.cmd.ready & can_read), axi.ar.ready.eq(port.cmd.ready & can_read),
port.cmd.we.eq(0), port.cmd.we.eq(0),
port.cmd.adr.eq(axi.ar.addr) port.cmd.adr.eq(axi.ar.addr >> ashift)
).Else( ).Else(
port.cmd.valid.eq(axi.aw.valid & can_write), port.cmd.valid.eq(axi.aw.valid & can_write),
axi.aw.ready.eq(port.cmd.ready & can_write), axi.aw.ready.eq(port.cmd.ready & can_write),
port.cmd.we.eq(1), port.cmd.we.eq(1),
port.cmd.adr.eq(axi.aw.addr) port.cmd.adr.eq(axi.aw.addr >> ashift)
) )
] ]