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Merge pull request #9 from felixheld/indentation-fixes 

Fix all remaining indentation issues in python code
This commit is contained in:
Tim Ansell 2018-01-13 13:38:02 +11:00 committed by GitHub
parent a09b7a05b8 72b1b109b7
commit 13d41f67ab
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 33 additions and 32 deletions
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39
litedram/phy/a7ddrphy.py
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@ -41,26 +41,27 @@ class A7DDRPHY(Module, AutoCSR):
# # # # # #
# Clock # Clock
sd_clk_se = Signal() for i in range(len(pads.clk_p)):
self.specials += [ sd_clk_se = Signal()
Instance("OSERDESE2", self.specials += [
p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1, Instance("OSERDESE2",
p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF", p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
p_SERDES_MODE="MASTER", p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
p_SERDES_MODE="MASTER",
o_OQ=sd_clk_se, o_OQ=sd_clk_se,
i_OCE=1, i_OCE=1,
i_RST=ResetSignal(), i_RST=ResetSignal(),
i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), i_CLK=ClockSignal("sys4x"), i_CLKDIV=ClockSignal(),
i_D1=0, i_D2=1, i_D3=0, i_D4=1, i_D1=0, i_D2=1, i_D3=0, i_D4=1,
i_D5=0, i_D6=1, i_D7=0, i_D8=1 i_D5=0, i_D6=1, i_D7=0, i_D8=1
), ),
Instance("OBUFDS", Instance("OBUFDS",
i_I=sd_clk_se, i_I=sd_clk_se,
o_O=pads.clk_p, o_O=pads.clk_p[i],
o_OB=pads.clk_n o_OB=pads.clk_n[i]
) )
] ]
# Addresses and commands # Addresses and commands
for i in range(addressbits): for i in range(addressbits):

24
setup.py
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@ -11,25 +11,25 @@ if sys.version_info[:3] < (3, 3):
setup( setup(
name="litedram", name="litedram",
version="0.1", version="0.1",
description="Small footprint and configurable dram core", description="Small footprint and configurable dram core",
long_description=open("README").read(), long_description=open("README").read(),
author="Florent Kermarrec", author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr", author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr", url="http://enjoy-digital.fr",
download_url="https://github.com/enjoy-digital/litedram", download_url="https://github.com/enjoy-digital/litedram",
test_suite="test", test_suite="test",
license="BSD", license="BSD",
platforms=["Any"], platforms=["Any"],
keywords="HDL ASIC FPGA hardware design", keywords="HDL ASIC FPGA hardware design",
classifiers=[ classifiers=[
"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
"Environment :: Console", "Environment :: Console",
"Development Status :: Alpha", "Development Status :: Alpha",
"Intended Audience :: Developers", "Intended Audience :: Developers",
"License :: OSI Approved :: BSD License", "License :: OSI Approved :: BSD License",
"Operating System :: OS Independent", "Operating System :: OS Independent",
"Programming Language :: Python", "Programming Language :: Python",
], ],
packages=find_packages(), packages=find_packages(),
include_package_data=True, include_package_data=True,

2
test/test_bist_async.py
View File

@ -75,7 +75,7 @@ def main_generator(dut):
checker = BISTDriver(dut.checker) checker = BISTDriver(dut.checker)
for i in range(16): for i in range(16):
yield yield
# write # write
yield from generator.reset() yield from generator.reset()