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frontend/fifo: Expose base/depth in bytes instead of DRAM's words.

This commit is contained in:
Florent Kermarrec 2021-10-06 14:47:34 +02:00
parent f3d01ce98c
commit 1598b2733a
1 changed files with 5 additions and 3 deletions
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8
litedram/frontend/fifo.py
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@ -224,6 +224,8 @@ class LiteDRAMFIFO(Module):
data_width_ratio = port_data_width//data_width data_width_ratio = port_data_width//data_width
if not with_bypass: if not with_bypass:
assert data_width_ratio == 1 assert data_width_ratio == 1
fifo_base = int(base/(port_data_width/8))
fifo_depth = int(depth/(port_data_width/8))
pre_fifo_depth = max( pre_fifo_depth, 2*data_width_ratio) pre_fifo_depth = max( pre_fifo_depth, 2*data_width_ratio)
post_fifo_depth = max(post_fifo_depth, 2*data_width_ratio) post_fifo_depth = max(post_fifo_depth, 2*data_width_ratio)
@ -238,8 +240,8 @@ class LiteDRAMFIFO(Module):
# DRAM-FIFO. # DRAM-FIFO.
self.submodules.dram_fifo = dram_fifo = _LiteDRAMFIFO( self.submodules.dram_fifo = dram_fifo = _LiteDRAMFIFO(
data_width = port_data_width, data_width = port_data_width,
base = base, base = fifo_base,
depth = depth, depth = fifo_depth,
write_port = write_port, write_port = write_port,
read_port = read_port, read_port = read_port,
) )
@ -300,7 +302,7 @@ class LiteDRAMFIFO(Module):
) )
dram_cnt_inc = Signal() dram_cnt_inc = Signal()
dram_cnt_dec = Signal() dram_cnt_dec = Signal()
dram_cnt = Signal(int(math.log2(depth + pre_fifo_depth + post_fifo_depth) + 1)) dram_cnt = Signal(int(math.log2(fifo_depth + pre_fifo_depth + post_fifo_depth) + 2))
self.sync += dram_cnt.eq(dram_cnt + dram_cnt_inc - dram_cnt_dec) self.sync += dram_cnt.eq(dram_cnt + dram_cnt_inc - dram_cnt_dec)
fsm.act("DRAM", fsm.act("DRAM",
# Increment DRAM Data Count on Pre-Converter's Sink cycle. # Increment DRAM Data Count on Pre-Converter's Sink cycle.