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examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)

This commit is contained in:
Florent Kermarrec 2018-09-05 09:13:28 +02:00
parent 1e64b7f492
commit 1652ab95c8
1 changed files with 11 additions and 3 deletions
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14
examples/litedram_gen.py
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@ -303,7 +303,9 @@ class LiteDRAMCore(SoCSDRAM):
if core_config["user_ports_type"] == "native": if core_config["user_ports_type"] == "native":
for i in range(core_config["user_ports_nb"]): for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port() user_port = self.sdram.crossbar.get_port()
platform.add_extension(get_native_user_port_ios(i, user_port.aw, user_port.dw)) platform.add_extension(get_native_user_port_ios(i,
user_port.address_width,
user_port.data_width))
_user_port_io = platform.request("user_port", i) _user_port_io = platform.request("user_port", i)
self.comb += [ self.comb += [
# cmd # cmd
@ -326,10 +328,16 @@ class LiteDRAMCore(SoCSDRAM):
elif core_config["user_ports_type"] == "axi": elif core_config["user_ports_type"] == "axi":
for i in range(core_config["user_ports_nb"]): for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port() user_port = self.sdram.crossbar.get_port()
axi_port = LiteDRAMAXIPort(user_port.dw, user_port.aw, 32) axi_port = LiteDRAMAXIPort(
user_port.data_width,
user_port.address_width + log2_int(user_port.data_width//8),
core_config["user_ports_id_width"])
axi2native = LiteDRAMAXI2Native(axi_port, user_port) axi2native = LiteDRAMAXI2Native(axi_port, user_port)
self.submodules += axi2native self.submodules += axi2native
platform.add_extension(get_axi_user_port_ios(i, user_port.aw, user_port.dw, 32)) platform.add_extension(get_axi_user_port_ios(i,
axi_port.address_width,
axi_port.data_width,
core_config["user_ports_id_width"]))
_axi_port_io = platform.request("user_port", i) _axi_port_io = platform.request("user_port", i)
self.comb += [ self.comb += [
# aw # aw