Merge pull request #42 from enjoy-digital/HalfRateSequentialFix

We wait an extra cycle for no reason
2018-09-23 15:04:42 +02:00 · 2018-09-23 15:04:42 +02:00 · 1777720a0c
parent c12404e00c 06c8c2afcf
commit 1777720a0c
1 changed files with 2 additions and 2 deletions
--- a/litedram/core/multiplexer.py
+++ b/litedram/core/multiplexer.py
@ -136,10 +136,10 @@ class tXXDController(Module):
        # # #

        if txxd is not None:
-            count = Signal(max=max(txxd+1, 2))
+            count = Signal(max=max(txxd, 2))
            self.sync += \
                If(valid,
-                    count.eq(txxd),
+                    count.eq(txxd-1),
                    If((txxd - 1) == 0,
                        ready.eq(1)
                    ).Else(