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Merge pull request #42 from enjoy-digital/HalfRateSequentialFix 

We wait an extra cycle for no reason
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enjoy-digital 2018-09-23 15:04:42 +02:00 committed by GitHub
parent c12404e00c 06c8c2afcf
commit 1777720a0c
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1 changed files with 2 additions and 2 deletions
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4
litedram/core/multiplexer.py
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@ -136,10 +136,10 @@ class tXXDController(Module):
# # # # # #
if txxd is not None: if txxd is not None:
count = Signal(max=max(txxd+1, 2)) count = Signal(max=max(txxd, 2))
self.sync += \ self.sync += \
If(valid, If(valid,
count.eq(txxd), count.eq(txxd-1),
If((txxd - 1) == 0, If((txxd - 1) == 0,
ready.eq(1) ready.eq(1)
).Else( ).Else(