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frontend/dma: Move ack of write responses and other cosmetic cleanups.

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This commit is contained in:
Florent Kermarrec 2021-11-29 13:22:11 +01:00
parent 925dbfd933
commit 17c19de8f8
1 changed files with 4 additions and 6 deletions
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10
litedram/frontend/dma.py
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@ -59,7 +59,7 @@ class LiteDRAMDMAReader(Module, AutoCSR):
# # #
# Native / AXI selection
# Native / AXI selection -------------------------------------------------------------------
is_native = isinstance(port, LiteDRAMNativePort)
is_axi = isinstance(port, LiteDRAMAXIPort)
if is_native:
@ -85,8 +85,8 @@ class LiteDRAMDMAReader(Module, AutoCSR):
]
# FIFO reservation level counter -----------------------------------------------------------
# incremented when data is planned to be queued
# decremented when data is dequeued
# - Incremented when data is planned to be queued.
# - Decremented when data is dequeued.
data_dequeued = Signal()
self.rsv_level = rsv_level = Signal(max=fifo_depth+1)
self.sync += [
@ -192,6 +192,7 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
(cmd, wdata) = port.cmd, port.wdata
elif is_axi:
(cmd, wdata) = port.aw, port.w
self.comb += port.b.ready.eq(1) # Always ack write responses.
else:
raise NotImplementedError
@ -221,9 +222,6 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
wdata.data.eq(fifo.source.data)
]
if is_axi:
self.comb += port.b.ready.eq(1)
if with_csr:
self.add_csr()