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phy/usddrphy: add cdly_value CSR to be able to read back configured clk/cmd delay.

This commit is contained in:
Florent Kermarrec 2020-03-10 12:31:19 +01:00
parent 26564ba93c
commit 183f1a6e27
1 changed files with 18 additions and 16 deletions
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34
litedram/phy/usddrphy.py
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@ -49,6 +49,7 @@ class USDDRPHY(Module, AutoCSR):
self._cdly_rst = CSR()
self._cdly_inc = CSR()
self._cdly_value = CSRStatus(9)
self._dly_sel = CSRStorage(databits//8)
@ -116,20 +117,21 @@ class USDDRPHY(Module, AutoCSR):
o_OQ = clk_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
p_DELAY_FORMAT = "TIME",
p_DELAY_TYPE = "VARIABLE",
p_DELAY_VALUE = 0,
i_RST = self._cdly_rst.re,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
i_ODATAIN = clk_o_nodelay,
o_DATAOUT = clk_o_delayed,
i_RST = self._cdly_rst.re,
i_CLK = ClockSignal(),
i_EN_VTC = self._en_vtc.storage,
i_CE = self._cdly_inc.re,
i_INC = 1,
o_CNTVALUEOUT = self._cdly_value.status,
i_ODATAIN = clk_o_nodelay,
o_DATAOUT = clk_o_delayed,
),
Instance("OBUFDS",
i_I = clk_o_delayed,
@ -159,7 +161,7 @@ class USDDRPHY(Module, AutoCSR):
o_OQ = a_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
@ -203,7 +205,7 @@ class USDDRPHY(Module, AutoCSR):
o_OQ = ba_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
@ -248,7 +250,7 @@ class USDDRPHY(Module, AutoCSR):
o_OQ = x_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
@ -298,7 +300,7 @@ class USDDRPHY(Module, AutoCSR):
o_OQ = dm_o_nodelay,
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
@ -354,7 +356,7 @@ class USDDRPHY(Module, AutoCSR):
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
@ -419,7 +421,7 @@ class USDDRPHY(Module, AutoCSR):
o_T_OUT = dq_t,
),
Instance("ISERDESE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_IS_CLK_INVERTED = 0,
p_IS_CLK_B_INVERTED = 1,
p_DATA_WIDTH = 8,
@ -432,7 +434,7 @@ class USDDRPHY(Module, AutoCSR):
o_Q = dq_bitslip.i,
),
Instance("ODELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,
@ -450,7 +452,7 @@ class USDDRPHY(Module, AutoCSR):
o_DATAOUT = dq_o_delayed,
),
Instance("IDELAYE3",
p_SIM_DEVICE = sim_device,
p_SIM_DEVICE = sim_device,
p_CASCADE = "NONE",
p_UPDATE_MODE = "ASYNC",
p_REFCLK_FREQUENCY = iodelay_clk_freq/1e6,