phy/usddrphy: add cdly_value CSR to be able to read back configured clk/cmd delay.

litedram/phy/usddrphy.py

@@ -49,6 +49,7 @@ class USDDRPHY(Module, AutoCSR):
 
         self._cdly_rst            = CSR()
         self._cdly_inc            = CSR()
+        self._cdly_value          = CSRStatus(9)
 
         self._dly_sel             = CSRStorage(databits//8)
 
@@ -128,6 +129,7 @@ class USDDRPHY(Module, AutoCSR):
                     i_EN_VTC       = self._en_vtc.storage,
                     i_CE           = self._cdly_inc.re,
                     i_INC          = 1,
+                    o_CNTVALUEOUT  = self._cdly_value.status,
                     i_ODATAIN      = clk_o_nodelay,
                     o_DATAOUT      = clk_o_delayed,
                 ),