litedram_gen: add more memtype asserts, remove csr_alignment (now fixed to 32-bit).
This commit is contained in:
Florent Kermarrec
parent
a595fe07f2
commit
1b56dcf364
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@ -212,6 +212,7 @@ class Platform(XilinxPlatform):
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class LiteDRAMECP5DDRPHYCRG(Module):
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def __init__(self, platform, core_config):
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assert core_config["memtype"] in ["DDR3"]
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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@ -255,13 +256,17 @@ class LiteDRAMECP5DDRPHYCRG(Module):
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class LiteDRAMS7DDRPHYCRG(Module):
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def __init__(self, platform, core_config):
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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self.clock_domains.cd_sys = ClockDomain()
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if core_config["memtype"] == "DDR3":
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if core_config["memtype"] == "DDR2":
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
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elif core_config["memtype"] == "DDR3":
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
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raise NotImplementedError
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self.clock_domains.cd_iodelay = ClockDomain()
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# # #
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@ -273,12 +278,15 @@ class LiteDRAMS7DDRPHYCRG(Module):
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self.comb += sys_pll.reset.eq(rst)
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sys_pll.register_clkin(clk, core_config["input_clk_freq"])
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sys_pll.create_clkout(self.cd_sys, core_config["sys_clk_freq"])
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if core_config["memtype"] == "DDR3":
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sys_pll.create_clkout(self.cd_sys4x, 4*core_config["sys_clk_freq"])
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if core_config["memtype"] == "DDR2":
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sys_pll.create_clkout(self.cd_sys2x, 2*core_config["sys_clk_freq"])
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sys_pll.create_clkout(self.cd_sys2x_dqs, 2*core_config["sys_clk_freq"], phase=90)
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elif core_config["memtype"] == "DDR3":
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sys_pll.create_clkout(self.cd_sys4x, 4*core_config["sys_clk_freq"])
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sys_pll.create_clkout(self.cd_sys4x_dqs, 4*core_config["sys_clk_freq"], phase=90)
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else:
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sys_pll.create_clkout(self.cd_sys2x, 2*core_config["sys_clk_freq"])
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sys_pll.create_clkout(self.cd_sys2x_dqs, 2*core_config["sys_clk_freq"], phase=90)
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raise NotImplementedError
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self.comb += platform.request("pll_locked").eq(sys_pll.locked)
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self.submodules.iodelay_pll = iodelay_pll = S7PLL(speedgrade=core_config["speedgrade"])
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@ -304,7 +312,6 @@ class LiteDRAMCore(SoCCore):
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sys_clk_freq = core_config["sys_clk_freq"]
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cpu_type = core_config["cpu"]
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cpu_variant = core_config.get("cpu_variant", "standard")
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csr_alignment = core_config.get("csr_alignment", 32)
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csr_data_width = core_config.get("csr_data_width", 8)
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if cpu_type is None:
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kwargs["integrated_rom_size"] = 0
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@ -318,7 +325,6 @@ class LiteDRAMCore(SoCCore):
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cpu_type = cpu_type,
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cpu_variant = cpu_variant,
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csr_data_width = csr_data_width,
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csr_alignment = csr_alignment,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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@ -331,8 +337,8 @@ class LiteDRAMCore(SoCCore):
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# DRAM -------------------------------------------------------------------------------------
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platform.add_extension(get_dram_ios(core_config))
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sdram_module = core_config["sdram_module"](sys_clk_freq,
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"1:4" if core_config["memtype"] == "DDR3" else "1:2")
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sdram_module = core_config["sdram_module"](sys_clk_freq, rate={"DDR3": "1:4", "DDR2": "1:2"}[core_config["memtype"]])
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# Sim
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if isinstance(platform, SimPlatform):
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from litex.tools.litex_sim import get_sdram_phy_settings
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@ -345,7 +351,8 @@ class LiteDRAMCore(SoCCore):
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module = sdram_module,
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settings = phy_settings,
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clk_freq = sdram_clk_freq)
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# ECP5DDRPHY
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# ECP5DDRPHY
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elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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assert core_config["memtype"] in ["DDR3"]
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self.submodules.ddrphy = core_config["sdram_phy"](
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@ -354,6 +361,7 @@ class LiteDRAMCore(SoCCore):
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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self.add_constant("ECP5DDRPHY")
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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# S7DDRPHY
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elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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@ -373,7 +381,7 @@ class LiteDRAMCore(SoCCore):
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self.add_csr("ddrphy")
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controller_settings = controller_settings = ControllerSettings(
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cmd_buffer_depth=core_config["cmd_buffer_depth"])
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cmd_buffer_depth = core_config["cmd_buffer_depth"])
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = sdram_module,
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@ -402,7 +410,7 @@ class LiteDRAMCore(SoCCore):
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# User ports -------------------------------------------------------------------------------
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self.comb += [
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platform.request("user_clk").eq(ClockSignal()),
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platform.request("user_rst").eq(ResetSignal())
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platform.request("user_rst").eq(ResetSignal()),
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]
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for name, port in core_config["user_ports"].items():
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# Native -------------------------------------------------------------------------------
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