Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litedram_gen/add_sdram: Remove origin: no longer required.

This commit is contained in:
Florent Kermarrec 2021-10-07 16:20:23 +02:00
parent f0a2f40a86
commit 1c59e77302
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
litedram/gen.py
View File

@ -621,7 +621,6 @@ class LiteDRAMCore(SoCCore):
self.add_sdram("sdram", self.add_sdram("sdram",
phy = sdram_phy, phy = sdram_phy,
module = sdram_module, module = sdram_module,
origin = self.mem_map["main_ram"],
size = 0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib. size = 0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib.
with_soc_interconnect = cpu_type is not None, with_soc_interconnect = cpu_type is not None,
l2_cache_size = 8, l2_cache_size = 8,