litedram_gen/add_sdram: Remove origin: no longer required.

2021-10-07 16:20:23 +02:00 · 2021-10-07 16:20:23 +02:00 · 1c59e77302
parent f0a2f40a86
commit 1c59e77302
1 changed files with 0 additions and 1 deletions
--- a/litedram/gen.py
+++ b/litedram/gen.py
@ -621,7 +621,6 @@ class LiteDRAMCore(SoCCore):
        self.add_sdram("sdram",
            phy                     = sdram_phy,
            module                  = sdram_module,
-            origin                  = self.mem_map["main_ram"],
            size                    = 0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib.
            with_soc_interconnect   = cpu_type is not None,
            l2_cache_size           = 8,