common/BitSlip: reset value to value.reset.
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@ -128,7 +128,7 @@ class BitSlip(Module):
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value = Signal(max=cycles*dw, reset=cycles*dw-1)
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self.sync += If(self.slp, value.eq(value + 1))
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self.sync += If(self.rst, value.eq(0))
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self.sync += If(self.rst, value.eq(value.reset))
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r = Signal((cycles+1)*dw, reset_less=True)
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self.sync += r.eq(Cat(r[dw:], self.i))
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