bench: cleanup, do more testing on 7-series.
This commit is contained in:
Florent Kermarrec
parent
f43cfad4e3
commit
1fb78fa558
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@ -119,9 +119,7 @@ def main():
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freq_max = 150e6,
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freq_step = 1e6,
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vco_freq = soc.crg.main_pll.compute_config()["vco"],
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bios_filename = "build/arty/software/bios/bios.bin",
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bios_timeout = 10,
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)
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bios_filename = "build/arty/software/bios/bios.bin")
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if __name__ == "__main__":
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main()
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316
bench/common.py
316
bench/common.py
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@ -4,141 +4,247 @@
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# PLL Helpers --------------------------------------------------------------------------------------
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class ClkReg1:
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def __init__(self, value=0):
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self.unpack(value)
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def unpack(self, value):
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self.low_time = (value >> 0) & (2**6 - 1)
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self.high_time = (value >> 6) & (2**6 - 1)
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self.reserved = (value >> 12) & (2**1 - 1)
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self.phase_mux = (value >> 13) & (2**3 - 1)
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def pack(self):
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value = (self.low_time << 0)
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value |= (self.high_time << 6)
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value |= (self.reserved << 12)
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value |= (self.phase_mux << 13)
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return value
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def __repr__(self):
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s = "ClkReg1:\n"
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s += " low_time: {:d}\n".format(self.low_time)
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s += " high_time: {:d}\n".format(self.high_time)
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s += " reserved: {:d}\n".format(self.reserved)
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s += " phase_mux: {:d}".format(self.phase_mux)
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return s
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class ClkReg2:
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def __init__(self, value=0):
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self.unpack(value)
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def unpack(self, value):
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self.delay_time = (value >> 0) & (2**6 - 1)
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self.no_count = (value >> 6) & (2**1 - 1)
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self.edge = (value >> 7) & (2**1 - 1)
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self.mx = (value >> 8) & (2**2 - 1)
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self.frac_wf_r = (value >> 10) & (2**1 - 1)
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self.frac_en = (value >> 11) & (2**1 - 1)
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self.frac = (value >> 12) & (2**3 - 1)
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self.reserved = (value >> 15) & (2**1 - 1)
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def pack(self):
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value = (self.delay_time << 0)
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value |= (self.no_count << 6)
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value |= (self.edge << 7)
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value |= (self.mx << 8)
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value |= (self.frac_wf_r << 10)
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value |= (self.frac_en << 11)
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value |= (self.frac << 12)
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value |= (self.reserved << 15)
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return value
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def __repr__(self):
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s = "ClkReg2:\n"
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s += " delay_time: {:d}\n".format(self.delay_time)
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s += " no_count: {:d}\n".format(self.no_count)
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s += " edge: {:d}\n".format(self.edge)
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s += " mx: {:d}\n".format(self.mx)
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s += " frac_wf_r: {:d}\n".format(self.frac_wf_r)
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s += " frac_en: {:d}\n".format(self.frac_en)
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s += " frac: {:d}\n".format(self.frac)
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s += " reserved: {:d}".format(self.reserved)
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return s
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class S7PLL:
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def __init__(self, bus):
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self.bus = bus
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def reset(self):
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self.bus.regs.crg_main_pll_drp_reset.write(1)
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def read(self, adr):
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self.bus.regs.crg_main_pll_drp_adr.write(adr)
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self.bus.regs.crg_main_pll_drp_read.write(1)
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return self.bus.regs.crg_main_pll_drp_dat_r.read()
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def write(self, adr, value):
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self.bus.regs.crg_main_pll_drp_adr.write(adr)
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self.bus.regs.crg_main_pll_drp_dat_w.write(value)
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self.bus.regs.crg_main_pll_drp_write.write(1)
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class USPLL:
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def __init__(self, bus):
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self.bus = bus
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def reset(self):
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self.bus.regs.crg_pll_drp_reset.write(1)
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def read(self, adr):
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self.bus.regs.crg_pll_drp_adr.write(adr)
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self.bus.regs.crg_pll_drp_read.write(1)
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return self.bus.regs.crg_pll_drp_dat_r.read()
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def write(self, adr, value):
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self.bus.regs.crg_pll_drp_adr.write(adr)
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self.bus.regs.crg_pll_drp_dat_w.write(value)
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self.bus.regs.crg_pll_drp_write.write(1)
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# Bench Controller ---------------------------------------------------------------------------------
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class BenchController:
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def __init__(self, bus):
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self.bus = bus
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def reboot(self):
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self.bus.regs.ctrl_reset.write(1)
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def load_rom(self, filename):
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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self.bus.write(self.bus.mems.rom.base + 4*i, data)
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# Bench Test ---------------------------------------------------------------------------------------
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def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=5):
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def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=10):
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import time
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from litex import RemoteClient
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wb = RemoteClient()
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wb.open()
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bus = RemoteClient()
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bus.open()
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# # #
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class SoCCtrl:
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@staticmethod
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def reboot():
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wb.regs.ctrl_reset.write(1)
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@staticmethod
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def load_rom(filename):
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from litex.soc.integration.common import get_mem_data
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rom_data = get_mem_data(filename, "little")
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for i, data in enumerate(rom_data):
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wb.write(wb.mems.rom.base + 4*i, data)
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class ClkReg1:
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def __init__(self, value=0):
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self.unpack(value)
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def unpack(self, value):
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self.low_time = (value >> 0) & (2**6 - 1)
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self.high_time = (value >> 6) & (2**6 - 1)
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self.reserved = (value >> 12) & (2**1 - 1)
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self.phase_mux = (value >> 13) & (2**3 - 1)
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def pack(self):
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value = (self.low_time << 0)
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value |= (self.high_time << 6)
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value |= (self.reserved << 12)
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value |= (self.phase_mux << 13)
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return value
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def __repr__(self):
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s = "ClkReg1:\n"
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s += " low_time: {:d}\n".format(self.low_time)
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s += " high_time: {:d}\n".format(self.high_time)
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s += " reserved: {:d}\n".format(self.reserved)
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s += " phase_mux: {:d}".format(self.phase_mux)
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return s
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class ClkReg2:
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def __init__(self, value = 0):
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self.unpack(value)
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def unpack(self, value):
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self.delay_time = (value >> 0) & (2**6 - 1)
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self.no_count = (value >> 6) & (2**1 - 1)
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self.edge = (value >> 7) & (2**1 - 1)
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self.mx = (value >> 8) & (2**2 - 1)
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self.frac_wf_r = (value >> 10) & (2**1 - 1)
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self.frac_en = (value >> 11) & (2**1 - 1)
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self.frac = (value >> 12) & (2**3 - 1)
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self.reserved = (value >> 15) & (2**1 - 1)
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def pack(self):
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value = (self.delay_time << 0)
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value |= (self.no_count << 6)
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value |= (self.edge << 7)
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value |= (self.mx << 8)
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value |= (self.frac_wf_r << 10)
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value |= (self.frac_en << 11)
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value |= (self.frac << 12)
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value |= (self.reserved << 15)
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return value
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def __repr__(self):
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s = "ClkReg2:\n"
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s += " delay_time: {:d}\n".format(self.delay_time)
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s += " no_count: {:d}\n".format(self.no_count)
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s += " edge: {:d}\n".format(self.edge)
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s += " mx: {:d}\n".format(self.mx)
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s += " frac_wf_r: {:d}\n".format(self.frac_wf_r)
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s += " frac_en: {:d}\n".format(self.frac_en)
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s += " frac: {:d}\n".format(self.frac)
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s += " reserved: {:d}".format(self.reserved)
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return s
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class S7PLL:
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def reset(self):
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wb.regs.crg_main_pll_drp_reset.write(1)
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def read(self, adr):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_read.write(1)
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return wb.regs.crg_main_pll_drp_dat_r.read()
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def write(self, adr, value):
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wb.regs.crg_main_pll_drp_adr.write(adr)
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wb.regs.crg_main_pll_drp_dat_w.write(value)
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wb.regs.crg_main_pll_drp_write.write(1)
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# # #
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ctrl = SoCCtrl()
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# Load BIOS and reboot SoC
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ctrl = BenchController(bus)
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ctrl.load_rom(bios_filename)
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ctrl.reboot()
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s7pll = S7PLL()
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x08))
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# PLL/ClkReg
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s7pll = S7PLL(bus)
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clkout0_clkreg1 = ClkReg1(s7pll.read(0x8))
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# Run calibration from freq_min to freq_max and log BIOS output.
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print("-"*80)
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print("Running calibration; sys_clk from {:3.3f}MHz to {:3.2f}MHz (step: {:3.2f}MHz)".format(
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freq_min/1e6, freq_max/1e6, freq_step/1e6))
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print("-"*80)
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print("")
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tested_vco_divs = []
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for clk_freq in range(int(freq_min), int(freq_max), int(freq_step)):
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# Compute VCO divider, skip if already tested.
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vco_div = int(vco_freq/clk_freq)
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if vco_div in tested_vco_divs:
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continue
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tested_vco_divs.append(vco_div)
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print("Reconfig Main PLL to {}MHz...".format(vco_freq/vco_div/1e6))
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print("-"*40)
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print("sys_clk = {}MHz...".format(vco_freq/vco_div/1e6))
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print("-"*40)
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# Reconfigure PLL to change sys_clk
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clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
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clkout0_clkreg1.low_time = vco_div//2
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s7pll.write(0x08, clkout0_clkreg1.pack())
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print("Measuring sys_clk...")
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# Measure/verify sys_clk
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duration = 5e-1
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start = wb.regs.crg_sys_clk_counter.read()
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start = bus.regs.crg_sys_clk_counter.read()
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time.sleep(duration)
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end = wb.regs.crg_sys_clk_counter.read()
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print("sys_clk: {:3.2f}MHz".format((end-start)/(1e6*duration)))
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end = bus.regs.crg_sys_clk_counter.read()
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print("Measured sys_clk: {:3.2f}MHz.".format((end-start)/(1e6*duration)))
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# Reboot SoC and log BIOS output
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print("-"*40)
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print("Reboot SoC and get BIOS log...")
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print("-"*40)
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ctrl.reboot()
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start = time.time()
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while (time.time() - start) < bios_timeout:
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if wb.regs.uart_xover_rxfull.read():
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for c in wb.read(wb.regs.uart_xover_rxtx.addr, 16, burst="fixed"):
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if bus.regs.uart_xover_rxfull.read():
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for c in bus.read(bus.regs.uart_xover_rxtx.addr, 16, burst="fixed"):
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print("{:c}".format(c), end="")
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print("")
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# # #
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wb.close()
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bus.close()
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# Bench Test ---------------------------------------------------------------------------------------
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def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=10):
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import time
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from litex import RemoteClient
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bus = RemoteClient()
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bus.open()
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# # #
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# Load BIOS and reboot SoC
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ctrl = BenchController(bus)
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#ctrl.load_rom(bios_filename)
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ctrl.reboot()
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# PLL/ClkReg
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uspll = USPLL(bus)
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clkout0_clkreg1 = ClkReg1(uspll.read(0x8))
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# Run calibration from freq_min to freq_max and log BIOS output.
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print("-"*80)
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print("Running calibration; sys_clk from {:3.3f}MHz to {:3.2f}MHz (step: {:3.2f}MHz)".format(
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freq_min/1e6, freq_max/1e6, freq_step/1e6))
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print("-"*80)
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print("")
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tested_vco_divs = []
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for clk_freq in range(int(freq_min), int(freq_max), int(freq_step)):
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# Compute VCO divider, skip if already tested.
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vco_div = int(vco_freq/(4*clk_freq))
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if vco_div in tested_vco_divs:
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continue
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tested_vco_divs.append(vco_div)
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print("-"*40)
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print("sys_clk = {}MHz...".format(vco_freq/4/vco_div/1e6))
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print("-"*40)
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# Reconfigure PLL to change sys_clk
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clkout0_clkreg1.high_time = vco_div//2 + vco_div%2
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clkout0_clkreg1.low_time = vco_div//2
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uspll.write(0x08, clkout0_clkreg1.pack())
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# Measure/verify sys_clk
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duration = 5e-1
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start = bus.regs.crg_sys_clk_counter.read()
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time.sleep(duration)
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end = bus.regs.crg_sys_clk_counter.read()
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print("Measured sys_clk: {:3.2f}MHz.".format((end-start)/(1e6*duration)))
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# Reboot SoC and log BIOS output
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print("-"*40)
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print("Reboot SoC and get BIOS log...")
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print("-"*40)
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ctrl.reboot()
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start = time.time()
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while (time.time() - start) < bios_timeout:
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if bus.regs.uart_xover_rxempty.read() == 0:
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for c in bus.read(bus.regs.uart_xover_rxtx.addr, 1, burst="fixed"):
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print("{:c}".format(c), end="")
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print("")
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# # #
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bus.close()
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@ -75,8 +75,7 @@ class BenchSoC(SoCCore):
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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cmd_latency = 1)
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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@ -118,9 +117,7 @@ def main():
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freq_max = 180e6,
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freq_step = 1e6,
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vco_freq = soc.crg.main_pll.compute_config()["vco"],
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bios_filename = "build/genesys2/software/bios/bios.bin",
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bios_timeout = 10,
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)
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bios_filename = "build/genesys2/software/bios/bios.bin")
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if __name__ == "__main__":
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main()
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@ -75,8 +75,7 @@ class BenchSoC(SoCCore):
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self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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cmd_latency = 1)
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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@ -85,7 +84,7 @@ class BenchSoC(SoCCore):
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)
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=500e3, cd="uart")
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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@ -118,9 +117,7 @@ def main():
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freq_max = 180e6,
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freq_step = 1e6,
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vco_freq = soc.crg.main_pll.compute_config()["vco"],
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bios_filename = "build/kc705/software/bios/bios.bin",
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bios_timeout = 10,
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)
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bios_filename = "build/kc705/software/bios/bios.bin")
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if __name__ == "__main__":
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main()
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@ -24,22 +24,22 @@ from litedram.phy import usddrphy
|
|||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
|
||||
class _CRG(Module):
|
||||
class _CRG(Module, AutoCSR):
|
||||
def __init__(self, platform, sys_clk_freq):
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
|
||||
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
|
||||
self.clock_domains.cd_clk200 = ClockDomain()
|
||||
self.clock_domains.cd_uart = ClockDomain()
|
||||
self.clock_domains.cd_uart = ClockDomain()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.pll = pll = USMMCM(speedgrade=-2)
|
||||
self.comb += pll.reset.eq(platform.request("cpu_reset"))
|
||||
pll.register_clkin(platform.request("clk125"), 125e6)
|
||||
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
|
||||
pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
|
||||
pll.create_clkout(self.cd_uart, 100e6)
|
||||
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
|
||||
pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
|
||||
pll.create_clkout(self.cd_uart, 100e6)
|
||||
pll.expose_drp()
|
||||
|
||||
self.specials += [
|
||||
|
|
@ -61,7 +61,7 @@ class _CRG(Module):
|
|||
# Bench SoC ----------------------------------------------------------------------------------------
|
||||
|
||||
class BenchSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=int(125e6)):
|
||||
def __init__(self, sys_clk_freq=int(175e6)):
|
||||
platform = kcu105.Platform()
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
|
|
@ -79,18 +79,17 @@ class BenchSoC(SoCCore):
|
|||
self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
|
||||
memtype = "DDR4",
|
||||
sys_clk_freq = sys_clk_freq,
|
||||
iodelay_clk_freq = 200e6,
|
||||
cmd_latency = 1)
|
||||
iodelay_clk_freq = 200e6)
|
||||
self.add_csr("ddrphy")
|
||||
self.add_sdram("sdram",
|
||||
phy = self.ddrphy,
|
||||
module = EDY4016A(sys_clk_freq, "1:4"),
|
||||
origin = self.mem_map["main_ram"],
|
||||
size = 0x40000000,
|
||||
phy = self.ddrphy,
|
||||
module = EDY4016A(sys_clk_freq, "1:4"),
|
||||
origin = self.mem_map["main_ram"],
|
||||
size = 0x40000000,
|
||||
)
|
||||
|
||||
# UARTBone ---------------------------------------------------------------------------------
|
||||
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=1e6, cd="uart")
|
||||
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
self.submodules.leds = LedChaser(
|
||||
|
|
@ -116,7 +115,13 @@ def main():
|
|||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||
|
||||
if args.test:
|
||||
raise NotImplementedError
|
||||
from common import us_bench_test
|
||||
us_bench_test(
|
||||
freq_min = 60e6,
|
||||
freq_max = 180e6,
|
||||
freq_step = 1e6,
|
||||
vco_freq = soc.crg.pll.compute_config()["vco"],
|
||||
bios_filename = "build/kcu105/software/bios/bios.bin")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
|
|||
Loading…
Reference in New Issue