frontend/bist: add dynamic random data and addressing
This commit is contained in:
Florent Kermarrec
parent
b13962c7bd
commit
209dc0d781
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@ -4,14 +4,15 @@ from functools import reduce
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from operator import xor
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from migen import *
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from migen.genlib.cdc import PulseSynchronizer, BusSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import PulseSynchronizer
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from migen.genlib.cdc import BusSynchronizer
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from litex.soc.interconnect.csr import *
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from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader
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@CEInserter()
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class LFSR(Module):
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"""Linear-Feedback Shift Register to generate a pseudo-random sequence.
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@ -26,10 +27,10 @@ class LFSR(Module):
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Attributes
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----------
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o : in
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o : out
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Output data
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"""
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def __init__(self, n_out, n_state=31, taps=[27, 30]):
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def __init__(self, n_out, n_state, taps):
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self.o = Signal(n_out)
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# # #
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@ -48,7 +49,6 @@ class LFSR(Module):
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]
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@CEInserter()
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class Counter(Module):
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"""Simple incremental counter.
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@ -59,7 +59,7 @@ class Counter(Module):
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Attributes
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----------
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o : in
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o : out
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Output data
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"""
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def __init__(self, n_out):
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@ -70,23 +70,69 @@ class Counter(Module):
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self.sync += self.o.eq(self.o + 1)
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@CEInserter()
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class Generator(Module):
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"""Address/Data Generator.
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Parameters
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----------
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n_out : int
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Width of the output data signal.
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Attributes
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----------
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random_enable : in
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Enable Random (LFSR)
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o : out
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Output data
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"""
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def __init__(self, n_out, n_state, taps):
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self.random_enable = Signal()
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self.o = Signal(n_out)
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# # #
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lfsr = LFSR(n_out, n_state, taps)
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count = Counter(n_out)
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self.submodules += lfsr, count
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self.comb += \
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If(self.random_enable,
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self.o.eq(lfsr.o)
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).Else(
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self.o.eq(count.o)
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)
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@ResetInserter()
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class _LiteDRAMBISTGenerator(Module):
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def __init__(self, dram_port, random):
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def __init__(self, dram_port):
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ashift = log2_int(dram_port.dw//8)
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awidth = dram_port.aw + ashift
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self.start = Signal()
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self.done = Signal()
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self.base = Signal(awidth)
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self.length = Signal(awidth)
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self.random_data_enable = Signal()
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self.random_addr_enable = Signal()
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self.ticks = Signal(32)
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# # #
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gen_cls = LFSR if random else Counter
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gen = gen_cls(min(dram_port.dw, 32)) # FIXME: remove lfsr limitation
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# data / address generators
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data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
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addr_gen = Generator(23, n_state=23, taps=[17, 22]) # PRBS23
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assert (23 + ashift) < awidth # addressing large enough for random
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self.submodules += data_gen, addr_gen
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self.comb += [
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data_gen.random_enable.eq(self.random_data_enable),
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addr_gen.random_enable.eq(self.random_addr_enable)
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]
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# dma
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dma = LiteDRAMDMAWriter(dram_port)
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self.submodules += dma, gen
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self.submodules += dma
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cmd_counter = Signal(dram_port.aw, reset_less=True)
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@ -102,7 +148,8 @@ class _LiteDRAMBISTGenerator(Module):
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fsm.act("RUN",
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dma.sink.valid.eq(1),
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If(dma.sink.ready,
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gen.ce.eq(1),
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data_gen.ce.eq(1),
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addr_gen.ce.eq(1),
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NextValue(cmd_counter, cmd_counter + 1),
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If(cmd_counter == (self.length[ashift:] - 1),
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NextState("DONE")
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@ -114,8 +161,8 @@ class _LiteDRAMBISTGenerator(Module):
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self.done.eq(1)
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)
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self.comb += [
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dma.sink.address.eq(self.base[ashift:] + cmd_counter),
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dma.sink.data.eq(gen.o)
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dma.sink.address.eq(self.base[ashift:] + addr_gen.o),
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dma.sink.data.eq(data_gen.o)
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]
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@ -126,21 +173,29 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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----------
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reset : in
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Reset the module.
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start : in
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Start the generation.
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base : in
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DRAM address to start from.
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length : in
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Number of DRAM words to write.
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done : out
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The module has completed writing the pattern.
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base : in
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DRAM address to start from.
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length : in
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Number of DRAM words to write.
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random_data_enable : in
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Enable random data (LFSR)
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random_addr_enable : in
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Enable random addressing (LFSR)
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ticks : out
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Duration of the generation.
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"""
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def __init__(self, dram_port, random=True):
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def __init__(self, dram_port):
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ashift = log2_int(dram_port.dw//8)
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awidth = dram_port.aw + ashift
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self.reset = CSR()
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@ -148,13 +203,15 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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self.done = CSRStatus()
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self.base = CSRStorage(awidth)
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self.length = CSRStorage(awidth)
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self.random_data_enable = CSRStorage()
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self.random_addr_enable = CSRStorage()
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self.ticks = CSRStatus(32)
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# # #
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cd = dram_port.cd
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core = _LiteDRAMBISTGenerator(dram_port, random)
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core = _LiteDRAMBISTGenerator(dram_port)
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core = ClockDomainsRenamer(cd)(core)
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self.submodules += core
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@ -187,6 +244,11 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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core.length.eq(length_sync.o)
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]
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self.specials += [
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MultiReg(self.random_data_enable.storage, core.random_data_enable, cd),
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MultiReg(self.random_addr_enable.storage, core.random_addr_enable, cd),
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]
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ticks_sync = BusSynchronizer(32, cd, "sys")
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self.submodules += ticks_sync
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self.comb += [
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@ -197,22 +259,33 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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@ResetInserter()
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class _LiteDRAMBISTChecker(Module, AutoCSR):
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def __init__(self, dram_port, random):
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def __init__(self, dram_port):
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ashift = log2_int(dram_port.dw//8)
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awidth = dram_port.aw + ashift
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self.start = Signal()
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self.done = Signal()
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self.base = Signal(awidth)
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self.length = Signal(awidth)
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self.random_data_enable = Signal()
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self.random_addr_enable = Signal()
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self.ticks = Signal(32)
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self.errors = Signal(32)
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# # #
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gen_cls = LFSR if random else Counter
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gen = gen_cls(min(dram_port.dw, 32)) # FIXME: remove lfsr limitation
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# data / address generators
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data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
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addr_gen = Generator(23, n_state=23, taps=[17, 22]) # PRBS23
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assert (23 + ashift) < awidth # addressing large enough for random
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self.submodules += data_gen, addr_gen
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self.comb += [
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data_gen.random_enable.eq(self.random_data_enable),
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addr_gen.random_enable.eq(self.random_addr_enable)
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]
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# dma
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dma = LiteDRAMDMAReader(dram_port)
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self.submodules += dma, gen
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self.submodules += dma
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# address
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cmd_counter = Signal(dram_port.aw, reset_less=True)
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@ -228,6 +301,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
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cmd_fsm.act("RUN",
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dma.sink.valid.eq(1),
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If(dma.sink.ready,
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addr_gen.ce.eq(1),
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NextValue(cmd_counter, cmd_counter + 1),
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If(cmd_counter == (self.length[ashift:] - 1),
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NextState("DONE")
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@ -235,7 +309,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
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)
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)
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cmd_fsm.act("DONE")
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self.comb += dma.sink.address.eq(self.base[ashift:] + cmd_counter)
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self.comb += dma.sink.address.eq(self.base[ashift:] + addr_gen.o)
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# data
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data_counter = Signal(dram_port.aw, reset_less=True)
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@ -253,9 +327,9 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
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data_fsm.act("RUN",
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dma.source.ready.eq(1),
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If(dma.source.valid,
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gen.ce.eq(1),
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data_gen.ce.eq(1),
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NextValue(data_counter, data_counter + 1),
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If(dma.source.data != gen.o,
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If(dma.source.data != data_gen.o,
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NextValue(self.errors, self.errors + 1)
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),
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If(data_counter == (self.length[ashift:] - 1),
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@ -279,13 +353,19 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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start : in
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Start the checking
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done : out
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The module has completed checking
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base : in
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DRAM address to start from.
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length : in
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Number of DRAM words to check.
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done : out
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The module has completed checking
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random_data_enable : in
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Enable random data (LFSR)
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random_addr_enable : in
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Enable random addressing (LFSR)
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ticks: out
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Duration of the check.
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@ -293,14 +373,16 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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errors : out
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Number of DRAM words which don't match.
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"""
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def __init__(self, dram_port, random=True):
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def __init__(self, dram_port):
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ashift = log2_int(dram_port.dw//8)
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awidth = dram_port.aw + ashift
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self.reset = CSR()
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self.start = CSR()
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self.done = CSRStatus()
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self.base = CSRStorage(awidth)
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self.length = CSRStorage(awidth)
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self.done = CSRStatus()
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self.random_data_enable = CSRStorage()
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self.random_addr_enable = CSRStorage()
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self.ticks = CSRStatus(32)
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self.errors = CSRStatus(32)
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@ -308,7 +390,7 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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cd = dram_port.cd
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core = _LiteDRAMBISTChecker(dram_port, random)
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core = _LiteDRAMBISTChecker(dram_port)
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core = ClockDomainsRenamer(cd)(core)
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self.submodules += core
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@ -341,6 +423,11 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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core.length.eq(length_sync.o)
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]
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self.specials += [
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MultiReg(self.random_data_enable.storage, core.random_data_enable, cd),
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MultiReg(self.random_addr_enable.storage, core.random_addr_enable, cd),
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]
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ticks_sync = BusSynchronizer(32, cd, "sys")
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self.submodules += ticks_sync
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self.comb += [
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