gen: change CSR config names, switch to csr_expose/csr_align

examples/arty.yml

@@ -34,5 +34,6 @@
     "user_ports_id_width": 32,    # AXI identifier width
 
     # CSR Port -----------------------------------------------------------------
-    "expose_csr_port": "no", # expose access to CSR (I/O) ports
+    "csr_expose": "no", # Expose CSR bus as I/Os
+    "csr_align" : 32,   # CSR alignment
 }

examples/genesys2.yml

@@ -34,5 +34,6 @@
     "user_ports_id_width": 32,    # AXI identifier width
 
     # CSR Port -----------------------------------------------------------------
-    "expose_csr_port": "no", # expose access to CSR (I/O) ports
+    "csr_expose": "no", # Expose CSR bus as I/Os
+    "csr_align" : 32,   # CSR alignment
 }

examples/nexys4ddr.yml

@@ -29,5 +29,6 @@
     "user_ports_id_width": 32,    # AXI identifier width
 
     # CSR Port -----------------------------------------------------------------
-    "expose_csr_port": "no", # expose access to CSR (I/O) ports
+    "csr_expose": "no", # Expose CSR bus as I/Os
+    "csr_align" : 32,   # CSR alignment
 }

litedram/gen.py

@@ -248,7 +248,7 @@ class LiteDRAMCore(SoCSDRAM):
     def __init__(self, platform, core_config, **kwargs):
         platform.add_extension(get_common_ios())
         sys_clk_freq = core_config["sys_clk_freq"]
-        csr_align = core_config.get("csr_port_align", 32)
+        csr_align = core_config.get("csr_align", 32)
         SoCSDRAM.__init__(self, platform, sys_clk_freq,
             cpu_type=core_config["cpu"],
             l2_size=16*core_config["sdram_module_nb"],
@@ -291,7 +291,7 @@ class LiteDRAMCore(SoCSDRAM):
         ]
 
         # CSR port
-        if core_config.get("expose_csr_port", "no") == "yes":
+        if core_config.get("csr_expose", "no") == "yes":
             csr_port = csr_bus.Interface(
                 address_width=self.csr_address_width,
                 data_width=self.csr_data_width)