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gen: change CSR config names, switch to csr_expose/csr_align

This commit is contained in:
Florent Kermarrec 2019-09-23 09:12:40 +02:00
parent da408a3982
commit 233191939e
4 changed files with 8 additions and 5 deletions
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3
examples/arty.yml
View File

@ -34,5 +34,6 @@
"user_ports_id_width": 32, # AXI identifier width "user_ports_id_width": 32, # AXI identifier width
# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"expose_csr_port": "no", # expose access to CSR (I/O) ports "csr_expose": "no", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment
} }

3
examples/genesys2.yml
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@ -34,5 +34,6 @@
"user_ports_id_width": 32, # AXI identifier width "user_ports_id_width": 32, # AXI identifier width
# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"expose_csr_port": "no", # expose access to CSR (I/O) ports "csr_expose": "no", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment
} }

3
examples/nexys4ddr.yml
View File

@ -29,5 +29,6 @@
"user_ports_id_width": 32, # AXI identifier width "user_ports_id_width": 32, # AXI identifier width
# CSR Port ----------------------------------------------------------------- # CSR Port -----------------------------------------------------------------
"expose_csr_port": "no", # expose access to CSR (I/O) ports "csr_expose": "no", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment
} }

4
litedram/gen.py
View File

@ -248,7 +248,7 @@ class LiteDRAMCore(SoCSDRAM):
def __init__(self, platform, core_config, **kwargs): def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios()) platform.add_extension(get_common_ios())
sys_clk_freq = core_config["sys_clk_freq"] sys_clk_freq = core_config["sys_clk_freq"]
csr_align = core_config.get("csr_port_align", 32) csr_align = core_config.get("csr_align", 32)
SoCSDRAM.__init__(self, platform, sys_clk_freq, SoCSDRAM.__init__(self, platform, sys_clk_freq,
cpu_type=core_config["cpu"], cpu_type=core_config["cpu"],
l2_size=16*core_config["sdram_module_nb"], l2_size=16*core_config["sdram_module_nb"],
@ -291,7 +291,7 @@ class LiteDRAMCore(SoCSDRAM):
] ]
# CSR port # CSR port
if core_config.get("expose_csr_port", "no") == "yes": if core_config.get("csr_expose", "no") == "yes":
csr_port = csr_bus.Interface( csr_port = csr_bus.Interface(
address_width=self.csr_address_width, address_width=self.csr_address_width,
data_width=self.csr_data_width) data_width=self.csr_data_width)