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core/multiplexer: use self.submodules for timing controllers, fix tFAW count

This commit is contained in:
Florent Kermarrec 2018-08-15 13:04:19 +02:00
parent db4ec67741
commit 23358b5d29
1 changed files with 5 additions and 9 deletions
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14
litedram/core/multiplexer.py
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@ -152,7 +152,7 @@ class tFAWController(Module):
count = Signal(max=tfaw) count = Signal(max=tfaw)
window = Signal(tfaw) window = Signal(tfaw)
self.sync += window.eq(Cat(valid, window)) self.sync += window.eq(Cat(valid, window))
self.comb += reduce(add, [window[i] for i in range(tfaw)]) self.comb += count.eq(reduce(add, [window[i] for i in range(tfaw)]))
self.sync += \ self.sync += \
If(count < 4, If(count < 4,
If(count == 3, If(count == 3,
@ -197,13 +197,11 @@ class Multiplexer(Module, AutoCSR):
self.submodules += steerer self.submodules += steerer
# tRRD timing (Row to Row delay) # tRRD timing (Row to Row delay)
self.trrdcon = trrdcon = tXXDController(settings.timing.tRRD) self.submodules.trrdcon = trrdcon = tXXDController(settings.timing.tRRD)
self.submodules += trrdcon
self.comb += trrdcon.valid.eq(choose_cmd.accept() & choose_cmd.activate()) self.comb += trrdcon.valid.eq(choose_cmd.accept() & choose_cmd.activate())
# tFAW timing (Four Activate Window) # tFAW timing (Four Activate Window)
self.tfawcon = tfawcon = tFAWController(settings.timing.tFAW) self.submodules.tfawcon = tfawcon = tFAWController(settings.timing.tFAW)
self.submodules += tfawcon
self.comb += tfawcon.valid.eq(choose_cmd.accept() & choose_cmd.activate()) self.comb += tfawcon.valid.eq(choose_cmd.accept() & choose_cmd.activate())
# RAS control # RAS control
@ -211,8 +209,7 @@ class Multiplexer(Module, AutoCSR):
self.comb += [bm.ras_allowed.eq(ras_allowed) for bm in bank_machines] self.comb += [bm.ras_allowed.eq(ras_allowed) for bm in bank_machines]
# tCCD timing (Column to Column delay) # tCCD timing (Column to Column delay)
self.tccdcon = tccdcon = tXXDController(settings.timing.tCCD) self.submodules.tccdcon = tccdcon = tXXDController(settings.timing.tCCD)
self.submodules += tccdcon
self.comb += tccdcon.valid.eq(choose_req.accept() & (choose_req.write() | choose_req.read())) self.comb += tccdcon.valid.eq(choose_req.accept() & (choose_req.write() | choose_req.read()))
# CAS control # CAS control
@ -220,11 +217,10 @@ class Multiplexer(Module, AutoCSR):
self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines] self.comb += [bm.cas_allowed.eq(cas_allowed) for bm in bank_machines]
# tWTR timing (Write to Read delay) # tWTR timing (Write to Read delay)
self.twtrcon = twtrcon = tXXDController( self.submodules.twtrcon = twtrcon = tXXDController(
settings.timing.tWTR + settings.timing.tWTR +
# tCCD must be added since tWTR begins after the transfer is complete # tCCD must be added since tWTR begins after the transfer is complete
settings.timing.tCCD if settings.timing.tCCD is not None else 0) settings.timing.tCCD if settings.timing.tCCD is not None else 0)
self.submodules += twtrcon
self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write()) self.comb += twtrcon.valid.eq(choose_req.accept() & choose_req.write())
# Read/write turnaround # Read/write turnaround