Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

modules: add DDR3 MT8KTF51264 SO-DIMM

This commit is contained in:
Florent Kermarrec 2019-09-09 08:47:19 +02:00
parent d37a30e0d7
commit 23ccdc9c0c
1 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
litedram/modules.py
View File

@ -375,6 +375,22 @@ class MT8JTF12864(SDRAMModule):
speedgrade_timings["default"] = speedgrade_timings["1333"]
class MT8KTF51264(SDRAMModule):
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 16384
ncols = 1024
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=(4, 10))
speedgrade_timings = {
"800": _SpeedgradeTimings(tRP=13.91, tRCD=13.91, tWR=13.91, tRFC=260, tFAW=(None, 50), tRAS=None),
"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRAS=None),
"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRAS=None),
}
speedgrade_timings["default"] = speedgrade_timings["1333"]
class MT18KSF1G72HZ(SDRAMModule):
memtype = "DDR3"
# geometry
@ -421,6 +437,7 @@ class MT16KTF1G64HZ(SDRAMModule):
}
speedgrade_timings["default"] = speedgrade_timings["1600"]
# DDR4 (Chips)
class EDY4016A(SDRAMModule):
memtype = "DDR4"