phys: integrate PHYPadsCombiner.

pads can now be passed to the PHY as:

# DRAM Chips with common command/address lines (traditional):
pads = platform.request("ddram")

# DRAM Chips with dissociated command/address lines:
pads = [platform.request("ddram", 0), platform.request("ddram", 1)]

LiteDRAM controller will automatically adapts itself to this combined pads.

litedram/phy/ecp5ddrphy.py

@@ -82,6 +82,7 @@ class ECP5DDRPHYInit(Module):
 
 class ECP5DDRPHY(Module, AutoCSR):
     def __init__(self, pads, sys_clk_freq=100e6):
+        pads        = PHYPadsCombiner(pads)
         memtype     = "DDR3"
         tck         = 2/(2*2*sys_clk_freq)
         addressbits = len(pads.a)
@@ -138,6 +139,10 @@ class ECP5DDRPHY(Module, AutoCSR):
 
         bl8_sel = Signal()
 
+        # Iterate on pads groups -------------------------------------------------------------------
+        for pads_group in range(len(pads.groups)):
+            pads.sel_group(pads_group)
+
             # Clock ------------------------------------------------------------------------------------
             for i in range(len(pads.clk_p)):
                 sd_clk_se = Signal()

litedram/phy/gensdrphy.py

@@ -18,13 +18,14 @@ from migen import *
 from migen.genlib.record import *
 from migen.fhdl.specials import Tristate
 
-from litedram.common import PhySettings
+from litedram.common import *
 from litedram.phy.dfi import *
 
 # Generic SDR PHY ----------------------------------------------------------------------------------
 
 class GENSDRPHY(Module):
     def __init__(self, pads, cl=2):
+        pads        = PHYPadsCombiner(pads)
         addressbits = len(pads.a)
         bankbits    = len(pads.ba)
         nranks      = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
@@ -52,7 +53,11 @@ class GENSDRPHY(Module):
 
         # # #
 
-        # Addresses and Commands -------------------------------------------------------------------
+        # Iterate on pads groups -------------------------------------------------------------------
+        for pads_group in range(len(pads.groups)):
+            pads.sel_group(pads_group)
+
+            # Addresses and Commands ---------------------------------------------------------------
             self.sync += [
                 pads.a.eq(dfi.p0.address),
                 pads.ba.eq(dfi.p0.bank),
@@ -70,14 +75,16 @@ class GENSDRPHY(Module):
         dq_oe = Signal()
         dq_i  = Signal(databits)
         self.sync += dq_o.eq(dfi.p0.wrdata)
-        self.specials += Tristate(pads.dq, dq_o, dq_oe, dq_i)
+        for i in range(len(pads.dq)):
+            self.specials += Tristate(pads.dq[i], dq_o[i], dq_oe, dq_i[i])
         if hasattr(pads, "dm"):
             assert len(pads.dm)*8 == databits
+            for i in range(len(pads.dm)):
                 self.sync += \
                     If(dfi.p0.wrdata_en,
-                    pads.dm.eq(dfi.p0.wrdata_mask)
+                        pads.dm[i].eq(dfi.p0.wrdata_mask)
                     ).Else(
-                    pads.dm.eq(0)
+                        pads.dm[i].eq(0)
                     )
         dq_in = Signal(databits)
         self.sync.sys_ps += dq_in.eq(dq_i)

litedram/phy/s6ddrphy.py

@@ -27,12 +27,13 @@ from migen import *
 from migen.genlib.record import *
 from migen.fhdl.decorators import ClockDomainsRenamer
 
-from litedram.common import PhySettings
+from litedram.common import *
 from litedram.phy.dfi import *
 
 
 class S6HalfRateDDRPHY(Module):
     def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
+        pads        = PHYPadsCombiner(pads)
         if memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
             raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
         addressbits = len(pads.a)
@@ -130,6 +131,10 @@ class S6HalfRateDDRPHY(Module):
                 r_dfi[n].we_n.eq(phase.we_n)
             ]
 
+        # Iterate on pads groups -------------------------------------------------------------------
+        for pads_group in range(len(pads.groups)):
+            pads.sel_group(pads_group)
+
             # output cmds
             sd_sdram_half += [
                 pads.a.eq(r_dfi[phase_sel].address),
@@ -406,6 +411,7 @@ class S6HalfRateDDRPHY(Module):
 
 class S6QuarterRateDDRPHY(Module):
     def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
+        pads        = PHYPadsCombiner(pads)
         addressbits = len(pads.a)
         bankbits = len(pads.ba)
         nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)

litedram/phy/s7ddrphy.py

@@ -25,6 +25,7 @@ class S7DDRPHY(Module, AutoCSR):
         iodelay_clk_freq = 200e6,
         cmd_latency      = 0):
         assert not (memtype == "DDR3" and nphases == 2) # FIXME: Needs BL8 support for nphases=2
+        pads        = PHYPadsCombiner(pads)
         tck         = 2/(2*nphases*sys_clk_freq)
         addressbits = len(pads.a)
         bankbits    = len(pads.ba)
@@ -93,7 +94,11 @@ class S7DDRPHY(Module, AutoCSR):
 
         # # #
 
-        # Clock ------------------------------------------------------------------------------------
+        # Iterate on pads groups -------------------------------------------------------------------
+        for pads_group in range(len(pads.groups)):
+            pads.sel_group(pads_group)
+
+            # Clock --------------------------------------------------------------------------------
             ddr_clk = "sys2x" if nphases == 2 else "sys4x"
             for i in range(len(pads.clk_p)):
                 sd_clk_se_nodelay = Signal()

litedram/phy/usddrphy.py

@@ -24,6 +24,7 @@ class USDDRPHY(Module, AutoCSR):
         iodelay_clk_freq = 200e6,
         cmd_latency      = 0,
         sim_device       = "ULTRASCALE"):
+        pads        = PHYPadsCombiner(pads)
         tck         = 2/(2*4*sys_clk_freq)
         addressbits = len(pads.a)
         if memtype == "DDR4":
@@ -93,6 +94,10 @@ class USDDRPHY(Module, AutoCSR):
 
         # # #
 
+        # Iterate on pads groups -------------------------------------------------------------------
+        for pads_group in range(len(pads.groups)):
+            pads.sel_group(pads_group)
+
             # Clock ------------------------------------------------------------------------------------
             clk_o_nodelay = Signal()
             clk_o_delayed = Signal()