test: add core.multiplexer._Steerer tests
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Jędrzej Boczar
parent
f36b5a4fd2
commit
26ce99320e
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@ -9,25 +9,33 @@ from litex.gen.sim import run_simulation
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from litex.soc.interconnect import stream
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from litedram.common import *
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from litedram.phy import dfi
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from litedram.core.multiplexer import _CommandChooser, _Steerer, Multiplexer
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from litedram.core.multiplexer import STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH
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class CmdRequestRWDriver:
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def __init__(self, req):
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def __init__(self, req, i=0, ep_layout=True, rw_layout=True):
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self.req = req
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self.rw_layout = rw_layout
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self.ep_layout = ep_layout
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self.bank = 0
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self.row = 0
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self.col = 0
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# used to distinguish commands
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self.bank = i
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self.row = i
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self.col = i
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def _drive(self, **kwargs):
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signals = [
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"valid", "first", "last",
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"a", "ba", "cas", "ras", "we",
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"is_cmd", "is_read", "is_write"
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]
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signals = ["a", "ba", "cas", "ras", "we",]
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if self.rw_layout:
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signals += ["is_cmd", "is_read", "is_write"]
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if self.ep_layout:
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signals += ["valid", "first", "last"]
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for s in signals:
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yield getattr(self.req, s).eq(kwargs.get(s, 0))
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# drive ba even for nop
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if "ba" not in kwargs:
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yield self.req.ba.eq(self.bank)
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def activate(self):
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yield from self._drive(valid=1, is_cmd=1, ras=1, a=self.row, ba=self.bank)
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@ -36,6 +44,9 @@ class CmdRequestRWDriver:
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a = 0 if not all_banks else (1 << 10)
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yield from self._drive(valid=1, is_cmd=1, ras=1, we=1, a=a, ba=self.bank)
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def refresh(self):
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yield from self._drive(valid=1, is_cmd=1, cas=1, ras=1, ba=self.bank)
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def write(self, auto_precharge=False):
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assert not (self.col & (1 << 10))
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col = self.col | (1 << 10) if auto_precharge else self.col
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@ -49,6 +60,7 @@ class CmdRequestRWDriver:
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def nop(self):
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yield from self._drive()
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# _CommandChooser ----------------------------------------------------------------------------------
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class CommandChooserDUT(Module):
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def __init__(self, n_requests, addressbits, bankbits):
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@ -56,12 +68,7 @@ class CommandChooserDUT(Module):
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for _ in range(n_requests)]
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self.submodules.chooser = _CommandChooser(self.requests)
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self.drivers = [CmdRequestRWDriver(req) for req in self.requests]
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# set known a/ba to easly distinguish currently connected request
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for i, driver in enumerate(self.drivers):
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driver.bank = i
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driver.row = i
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driver.col = i
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self.drivers = [CmdRequestRWDriver(req, i) for i, req in enumerate(self.requests)]
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def set_requests(self, description):
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assert len(description) == len(self.drivers)
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@ -265,3 +272,220 @@ class TestCommandChooser(unittest.TestCase):
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requests = "pr_aa_pw"
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order = "0670670"
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self.selection_test(requests, order, wants=["want_cmds", "want_writes"])
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# _Steerer -----------------------------------------------------------------------------------------
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class SteererDUT(Module):
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def __init__(self, nranks, databits, nphases):
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a, ba = 13, 3
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nop = Record(cmd_request_layout(a=a, ba=ba))
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choose_cmd = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
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choose_req = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
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refresher_cmd = stream.Endpoint(cmd_request_rw_layout(a=a, ba=ba))
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self.commands = [nop, choose_cmd, choose_req, refresher_cmd]
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self.dfi = dfi.Interface(addressbits=a, bankbits=ba, nranks=nranks, databits=databits,
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nphases=nphases)
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self.submodules.steerer = _Steerer(self.commands, self.dfi)
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# nop is not an endpoint and does not have is_* signals
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self.drivers = [CmdRequestRWDriver(req, i, ep_layout=i != 0, rw_layout=i != 0)
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for i, req in enumerate(self.commands)]
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class TestSteerer(unittest.TestCase):
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def test_nop_not_valid(self):
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def main_generator(dut):
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# nop on both phases
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yield dut.steerer.sel[0].eq(STEER_NOP)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield from dut.drivers[0].nop()
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yield
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for i in range(2):
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cas_n = (yield dut.dfi.phases[i].cas_n)
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ras_n = (yield dut.dfi.phases[i].ras_n)
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we_n = (yield dut.dfi.phases[i].we_n)
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# nop should have cas_n/ras_n/we_n = (1, 1, 1)
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self.assertEqual((cas_n, ras_n, we_n), (1, 1, 1))
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dut = SteererDUT(nranks=2, databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_connect_only_if_valid_and_ready(self):
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def main_generator(dut):
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# set possible requests
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_CMD].activate()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_REFRESH].refresh()
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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yield
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def check(is_ready):
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# cmd on phase 0 should be STEER_CMD=activate
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p = dut.dfi.phases[0]
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self.assertEqual((yield p.bank), STEER_CMD)
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self.assertEqual((yield p.address), STEER_CMD)
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if is_ready:
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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else: # not steered
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 1)
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self.assertEqual((yield p.we_n), 1)
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# nop on phase 1 should be STEER_NOP
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p = dut.dfi.phases[1]
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 1)
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self.assertEqual((yield p.we_n), 1)
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yield from check(is_ready=False)
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yield dut.commands[STEER_CMD].ready.eq(1)
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yield
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yield
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yield from check(is_ready=True)
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dut = SteererDUT(nranks=2, databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_no_decode_ba_signle_rank(self):
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def main_generator(dut):
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_REFRESH].refresh()
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# all the bits are for bank
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dut.drivers[STEER_CMD].bank = 0b110
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yield from dut.drivers[STEER_CMD].activate()
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yield dut.commands[STEER_CMD].ready.eq(1)
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_NOP)
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yield dut.steerer.sel[1].eq(STEER_CMD)
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yield
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yield
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p = dut.dfi.phases[1]
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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self.assertEqual((yield p.address), STEER_CMD)
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self.assertEqual((yield p.bank), 0b110)
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self.assertEqual((yield p.cs_n), 0)
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dut = SteererDUT(nranks=1, databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_decode_ba_multiple_ranks(self):
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def main_generator(dut):
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_REFRESH].refresh()
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_NOP)
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yield dut.steerer.sel[1].eq(STEER_CMD)
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variants = [
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# ba, phase.bank, phase.cs_n
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(0b110, 0b10, 0b01), # rank=1 -> cs=0b10 -> cs_n=0b01
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(0b101, 0b01, 0b01), # rank=1 -> cs=0b10 -> cs_n=0b01
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(0b001, 0b01, 0b10), # rank=0 -> cs=0b01 -> cs_n=0b10
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]
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for ba, phase_bank, phase_cs_n in variants:
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with self.subTest(ba=ba):
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# 1 bit for rank, 2 bits for bank
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dut.drivers[STEER_CMD].bank = ba
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yield from dut.drivers[STEER_CMD].activate()
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yield dut.commands[STEER_CMD].ready.eq(1)
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yield
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yield
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p = dut.dfi.phases[1]
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self.assertEqual((yield p.cas_n), 1)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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self.assertEqual((yield p.bank), phase_bank)
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self.assertEqual((yield p.cs_n), phase_cs_n)
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dut = SteererDUT(nranks=2, databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_select_all_ranks_on_refresh(self):
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def main_generator(dut):
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yield from dut.drivers[STEER_NOP].nop()
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yield from dut.drivers[STEER_REQ].write()
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yield from dut.drivers[STEER_CMD].activate()
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# set how phases are steered
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yield dut.steerer.sel[0].eq(STEER_REFRESH)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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variants = [
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# ba, phase.bank, phase.cs_n (always all enabled)
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(0b110, 0b10, 0b00),
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(0b101, 0b01, 0b00),
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(0b001, 0b01, 0b00),
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]
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for ba, phase_bank, phase_cs_n in variants:
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with self.subTest(ba=ba):
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# 1 bit for rank, 2 bits for bank
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dut.drivers[STEER_REFRESH].bank = ba
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yield from dut.drivers[STEER_REFRESH].refresh()
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yield dut.commands[STEER_REFRESH].ready.eq(1)
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yield
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yield
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p = dut.dfi.phases[0]
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self.assertEqual((yield p.cas_n), 0)
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self.assertEqual((yield p.ras_n), 0)
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self.assertEqual((yield p.we_n), 1)
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self.assertEqual((yield p.bank), phase_bank)
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self.assertEqual((yield p.cs_n), phase_cs_n)
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dut = SteererDUT(nranks=2, databits=16, nphases=2)
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run_simulation(dut, main_generator(dut))
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def test_reset_n_high(self):
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def main_generator(dut):
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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self.assertEqual((yield dut.dfi.phases[0].reset_n), 1)
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self.assertEqual((yield dut.dfi.phases[1].reset_n), 1)
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self.assertEqual((yield dut.dfi.phases[2].reset_n), 1)
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self.assertEqual((yield dut.dfi.phases[3].reset_n), 1)
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dut = SteererDUT(nranks=2, databits=16, nphases=4)
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run_simulation(dut, main_generator(dut))
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def test_cke_high_all_ranks(self):
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def main_generator(dut):
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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self.assertEqual((yield dut.dfi.phases[0].cke), 0b11)
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self.assertEqual((yield dut.dfi.phases[1].cke), 0b11)
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self.assertEqual((yield dut.dfi.phases[2].cke), 0b11)
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self.assertEqual((yield dut.dfi.phases[3].cke), 0b11)
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dut = SteererDUT(nranks=2, databits=16, nphases=4)
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run_simulation(dut, main_generator(dut))
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def test_odt_high_all_ranks(self):
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def main_generator(dut):
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yield dut.steerer.sel[0].eq(STEER_CMD)
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yield dut.steerer.sel[1].eq(STEER_NOP)
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yield
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self.assertEqual((yield dut.dfi.phases[0].odt), 0b11)
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self.assertEqual((yield dut.dfi.phases[1].odt), 0b11)
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self.assertEqual((yield dut.dfi.phases[2].odt), 0b11)
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self.assertEqual((yield dut.dfi.phases[3].odt), 0b11)
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dut = SteererDUT(nranks=2, databits=16, nphases=4)
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run_simulation(dut, main_generator(dut))
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