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litedram
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modules: add MT18KSF1G72HZ_1G6

This commit is contained in:
Florent Kermarrec 2018-06-12 09:54:38 +02:00
parent c23814961d
commit 2bd7707e67
1 changed files with 15 additions and 0 deletions
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15
litedram/modules.py
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@ -247,3 +247,18 @@ class MT41J256M16(SDRAMModule):
tWTR = 8 tWTR = 8
tREFI = 64*1000*1000/8192 tREFI = 64*1000*1000/8192
tRFC = 260 tRFC = 260
class MT18KSF1G72HZ_1G6(SDRAMModule):
memtype = "DDR3"
# geometry
nbanks = 8
nrows = 65536
ncols = 1024
# timings (-125 speedgrade)
tRP = 13.75
tRCD = 13.75
tWR = 15
tWTR = 8
tREFI = 64*1000*1000/8192
tRFC = 260