litedram/sdram_init/ddr4: disable data mask (not required)
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@ -320,7 +320,7 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = 0
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mr4 = 0
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mr5 = 1 << 10 # data mask enable
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mr5 = 0
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mr6 = format_mr6(4) # FIXME: tCCD
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init_sequence = [
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