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modules: add Insignis NDS36PT5 

add Insignis NDS36PT5.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
Fin Maaß 2024-06-13 12:09:48 +02:00
parent 7dacfaf684
commit 2d5a66f644
1 changed files with 9 additions and 0 deletions
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litedram/modules.py
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@ -544,6 +544,15 @@ class M12L16161A(SDRModule):
technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10)) technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
class NDS36PT5(SDRModule):
# geometry
nbanks = 4
nrows = 8192
ncols = 512
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(2, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=10, tRFC=(None, 55), tFAW=None, tRAS=40)}
class W9825G6KH6(SDRModule): class W9825G6KH6(SDRModule):
# geometry # geometry
nbanks = 4 nbanks = 4